This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Tested-by: Paweł Chmiel <[email protected]>
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index 000000000000..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar <[email protected]>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: phy-pma
+
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+ };
+...
base-commit: aab2003999e78bbf2058dae1e661c44ede1d9766
--
2.17.1
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
[Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
Reported-by: kernel test robot <[email protected]>
Reviewed-by: Kiwoong Kim <[email protected]>
Signed-off-by: Seungwon Jeon <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Vinod Koul <[email protected]>
Tested-by: Paweł Chmiel <[email protected]>
---
- Changes V11 -> V12
* Fixed kernel test robot warnings
- Changes V10 -> V11
* Addressed review comments from Vinod
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++++++
drivers/phy/samsung/phy-samsung-ufs.c | 359 ++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.h | 139 ++++++++++
5 files changed, 594 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index 000000000000..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = exynos7_pre_init_cfg,
+ [CFG_POST_INIT] = exynos7_post_init_cfg,
+ [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
+};
+
+static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
+ .cfg = exynos7_ufs_phy_cfgs,
+ .isol = {
+ .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+ .has_symbol_clk = 1,
+};
+
+#endif /* _PHY_EXYNOS7_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
new file mode 100644
index 000000000000..3077f3901737
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver for Samsung SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <[email protected]>
+ * Author: Alim Akhtar <[email protected]>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "phy-samsung-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
+ const struct samsung_ufs_phy_cfg *cfg,
+ u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ const unsigned int timeout_us = 100000;
+ const unsigned int sleep_us = 10;
+ u32 val;
+ int err;
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
+ val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy pll lock acquisition %d\n", err);
+ goto out;
+ }
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
+ if (err)
+ dev_err(ufs_phy->dev,
+ "failed to get phy cdr lock acquisition %d\n", err);
+out:
+ return err;
+}
+
+static int samsung_ufs_phy_calibrate(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct samsung_ufs_phy_cfg *cfg;
+ int err = 0;
+ int i;
+
+ if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
+ ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[ufs_phy->ufs_phy_state];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ samsung_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+ if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
+ err = samsung_ufs_phy_wait_for_lock_acq(phy);
+
+ /**
+ * In Samsung ufshci, PHY need to be calibrated at different
+ * stages / state mainly before Linkstartup, after Linkstartup,
+ * before power mode change and after power mode change.
+ * Below state machine to make sure to calibrate PHY in each
+ * state. Here after configuring PHY in a given state, will
+ * change the state to next state so that next state phy
+ * calibration value can be programed
+ */
+ switch (ufs_phy->ufs_phy_state) {
+ case CFG_PRE_INIT:
+ ufs_phy->ufs_phy_state = CFG_POST_INIT;
+ break;
+ case CFG_POST_INIT:
+ ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
+ break;
+ case CFG_PRE_PWR_HS:
+ ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
+ break;
+ case CFG_POST_PWR_HS:
+ /* Change back to INIT state */
+ ufs_phy->ufs_phy_state = CFG_PRE_INIT;
+ break;
+ default:
+ dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
+ }
+
+out:
+ return err;
+}
+
+static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
+{
+ int ret = 0;
+
+ phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
+ if (IS_ERR(phy->tx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
+ goto out;
+ }
+
+ phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
+ if (IS_ERR(phy->rx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
+ goto out;
+ }
+
+ phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
+ if (IS_ERR(phy->rx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
+ goto out;
+ }
+
+ ret = clk_prepare_enable(phy->tx0_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
+ goto out;
+ }
+
+ ret = clk_prepare_enable(phy->rx0_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
+ clk_disable_unprepare(phy->tx0_symbol_clk);
+ goto out;
+ }
+
+ ret = clk_prepare_enable(phy->rx1_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
+ clk_disable_unprepare(phy->tx0_symbol_clk);
+ clk_disable_unprepare(phy->rx0_symbol_clk);
+ }
+out:
+ return ret;
+}
+
+static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
+{
+ int ret;
+
+ phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
+ if (IS_ERR(phy->ref_clk))
+ dev_err(phy->dev, "failed to get ref_clk clock\n");
+
+ ret = clk_prepare_enable(phy->ref_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
+ return ret;
+ }
+
+ dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
+
+ return 0;
+}
+
+static int samsung_ufs_phy_init(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+ int ret;
+
+ _phy->lane_cnt = phy->attrs.bus_width;
+ _phy->ufs_phy_state = CFG_PRE_INIT;
+
+ if (_phy->drvdata->has_symbol_clk) {
+ ret = samsung_ufs_phy_symbol_clk_init(_phy);
+ if (ret)
+ dev_err(_phy->dev, "failed to set ufs phy symbol clocks\n");
+ }
+
+ ret = samsung_ufs_phy_clks_init(_phy);
+ if (ret)
+ dev_err(_phy->dev, "failed to set ufs phy clocks\n");
+
+ samsung_ufs_phy_calibrate(phy);
+
+ return 0;
+}
+
+static int samsung_ufs_phy_power_on(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+
+ samsung_ufs_phy_ctrl_isol(_phy, false);
+ return 0;
+}
+
+static int samsung_ufs_phy_power_off(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+
+ samsung_ufs_phy_ctrl_isol(_phy, true);
+ return 0;
+}
+
+static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
+ enum phy_mode mode, int submode)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(generic_phy);
+
+ _phy->mode = PHY_MODE_INVALID;
+
+ if (mode > 0)
+ _phy->mode = mode;
+
+ return 0;
+}
+
+static int samsung_ufs_phy_exit(struct phy *phy)
+{
+ struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
+
+ clk_disable_unprepare(_phy->ref_clk);
+
+ if (_phy->drvdata->has_symbol_clk) {
+ clk_disable_unprepare(_phy->tx0_symbol_clk);
+ clk_disable_unprepare(_phy->rx0_symbol_clk);
+ clk_disable_unprepare(_phy->rx1_symbol_clk);
+ }
+
+ return 0;
+}
+
+static struct phy_ops samsung_ufs_phy_ops = {
+ .init = samsung_ufs_phy_init,
+ .exit = samsung_ufs_phy_exit,
+ .power_on = samsung_ufs_phy_power_on,
+ .power_off = samsung_ufs_phy_power_off,
+ .calibrate = samsung_ufs_phy_calibrate,
+ .set_mode = samsung_ufs_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id samsung_ufs_phy_match[];
+
+static int samsung_ufs_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match;
+ struct samsung_ufs_phy *phy;
+ struct phy *gen_phy;
+ struct phy_provider *phy_provider;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ int err = 0;
+
+ match = of_match_node(samsung_ufs_phy_match, dev->of_node);
+ if (!match) {
+ err = -EINVAL;
+ dev_err(dev, "failed to get match_node\n");
+ goto out;
+ }
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
+ if (IS_ERR(phy->reg_pma)) {
+ err = PTR_ERR(phy->reg_pma);
+ goto out;
+ }
+
+ phy->reg_pmu = syscon_regmap_lookup_by_phandle(
+ dev->of_node, "samsung,pmu-syscon");
+ if (IS_ERR(phy->reg_pmu)) {
+ err = PTR_ERR(phy->reg_pmu);
+ dev_err(dev, "failed syscon remap for pmu\n");
+ goto out;
+ }
+
+ gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
+ if (IS_ERR(gen_phy)) {
+ err = PTR_ERR(gen_phy);
+ dev_err(dev, "failed to create PHY for ufs-phy\n");
+ goto out;
+ }
+
+ drvdata = match->data;
+ phy->dev = dev;
+ phy->drvdata = drvdata;
+ phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
+ phy->isol = &drvdata->isol;
+ phy->lane_cnt = PHY_DEF_LANE_CNT;
+
+ phy_set_drvdata(gen_phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ err = PTR_ERR(phy_provider);
+ dev_err(dev, "failed to register phy-provider\n");
+ goto out;
+ }
+out:
+ return err;
+}
+
+static const struct of_device_id samsung_ufs_phy_match[] = {
+ {
+ .compatible = "samsung,exynos7-ufs-phy",
+ .data = &exynos7_ufs_phy,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
+
+static struct platform_driver samsung_ufs_phy_driver = {
+ .probe = samsung_ufs_phy_probe,
+ .driver = {
+ .name = "samsung-ufs-phy",
+ .of_match_table = samsung_ufs_phy_match,
+ },
+};
+module_platform_driver(samsung_ufs_phy_driver);
+MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
+MODULE_AUTHOR("Seungwon Jeon <[email protected]>");
+MODULE_AUTHOR("Alim Akhtar <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
new file mode 100644
index 000000000000..5de78710524c
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <[email protected]>
+ * Author: Alim Akhtar <[email protected]>
+ *
+ */
+#ifndef _PHY_SAMSUNG_UFS_
+#define _PHY_SAMSUNG_UFS_
+
+#define PHY_COMN_BLK 1
+#define PHY_TRSV_BLK 2
+#define END_UFS_PHY_CFG { 0 }
+#define PHY_TRSV_CH_OFFSET 0x30
+#define PHY_APB_ADDR(off) ((off) << 2)
+
+#define PHY_COMN_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = 0, \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_COMN_BLK, \
+}
+
+#define PHY_TRSV_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_TRSV_BLK, \
+}
+
+/* UFS PHY registers */
+#define PHY_PLL_LOCK_STATUS 0x1e
+#define PHY_CDR_LOCK_STATUS 0x5e
+
+#define PHY_PLL_LOCK_BIT BIT(5)
+#define PHY_CDR_LOCK_BIT BIT(4)
+
+/* description for PHY calibration */
+enum {
+ /* applicable to any */
+ PWR_DESC_ANY = 0,
+ /* mode */
+ PWR_DESC_PWM = 1,
+ PWR_DESC_HS = 2,
+ /* series */
+ PWR_DESC_SER_A = 1,
+ PWR_DESC_SER_B = 2,
+ /* gear */
+ PWR_DESC_G1 = 1,
+ PWR_DESC_G2 = 2,
+ PWR_DESC_G3 = 3,
+ /* field mask */
+ MD_MASK = 0x3,
+ SR_MASK = 0x3,
+ GR_MASK = 0x7,
+};
+
+#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
+#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
+#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
+#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
+#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
+#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_PWM)
+#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | PWR_DESC_HS)
+#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_HS)
+#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_ANY)
+/* PHY calibration point/state */
+enum {
+ CFG_PRE_INIT,
+ CFG_POST_INIT,
+ CFG_PRE_PWR_HS,
+ CFG_POST_PWR_HS,
+ CFG_TAG_MAX,
+};
+
+struct samsung_ufs_phy_cfg {
+ u32 off_0;
+ u32 off_1;
+ u32 val;
+ u8 desc;
+ u8 id;
+};
+
+struct samsung_ufs_phy_drvdata {
+ const struct samsung_ufs_phy_cfg **cfg;
+ struct pmu_isol {
+ u32 offset;
+ u32 mask;
+ u32 en;
+ } isol;
+ bool has_symbol_clk;
+};
+
+struct samsung_ufs_phy {
+ struct device *dev;
+ void __iomem *reg_pma;
+ struct regmap *reg_pmu;
+ struct clk *ref_clk;
+ struct clk *ref_clk_parent;
+ struct clk *tx0_symbol_clk;
+ struct clk *rx0_symbol_clk;
+ struct clk *rx1_symbol_clk;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ struct samsung_ufs_phy_cfg **cfg;
+ const struct pmu_isol *isol;
+ u8 lane_cnt;
+ int ufs_phy_state;
+ enum phy_mode mode;
+};
+
+static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
+{
+ return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static inline void samsung_ufs_phy_ctrl_isol(
+ struct samsung_ufs_phy *phy, u32 isol)
+{
+ regmap_update_bits(phy->reg_pmu, phy->isol->offset,
+ phy->isol->mask, isol ? 0 : phy->isol->en);
+}
+
+#include "phy-exynos7-ufs.h"
+
+#endif /* _PHY_SAMSUNG_UFS_ */
--
2.17.1
Hi Vinod
Gentle Reminder !!
On Fri, Jul 3, 2020 at 11:02 PM Alim Akhtar <[email protected]> wrote:
>
> This patch introduces Samsung UFS PHY driver. This driver
> supports to deal with phy calibration and power control
> according to UFS host driver's behavior.
>
> [Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
> Reported-by: kernel test robot <[email protected]>
> Reviewed-by: Kiwoong Kim <[email protected]>
> Signed-off-by: Seungwon Jeon <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Tested-by: Paweł Chmiel <[email protected]>
> ---
> - Changes V11 -> V12
> * Fixed kernel test robot warnings
>
> - Changes V10 -> V11
> * Addressed review comments from Vinod
>
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++++++
> drivers/phy/samsung/phy-samsung-ufs.c | 359 ++++++++++++++++++++++++++
> drivers/phy/samsung/phy-samsung-ufs.h | 139 ++++++++++
> 5 files changed, 594 insertions(+)
> create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index 19f2e3119343..e20d2fcc9fe7 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
> Enable PCIe PHY support for Exynos SoC series.
> This driver provides PHY interface for Exynos PCIe controller.
>
> +config PHY_SAMSUNG_UFS
> + tristate "SAMSUNG SoC series UFS PHY driver"
> + depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the Samsung UFS PHY driver for
> + Samsung SoCs. This driver provides the interface for UFS
> + host controller to do PHY related programming.
> +
> config PHY_SAMSUNG_USB2
> tristate "Samsung USB 2.0 PHY driver"
> depends on HAS_IOMEM
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index db9b1aa0de6e..3959100fe8a2 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> +obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
> obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
> phy-exynos-usb2-y += phy-samsung-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h
> new file mode 100644
> index 000000000000..c4aab792d30e
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver data for Samsung EXYNOS7 SoC
> + *
> + * Copyright (C) 2020 Samsung Electronics Co., Ltd.
> + */
> +#ifndef _PHY_EXYNOS7_UFS_H_
> +#define _PHY_EXYNOS7_UFS_H_
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +
> +/* Calibration for phy initialization */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
> + END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> + END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
> + /* Setting order: 1st(0x16, 2nd(0x15) */
> + PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
> + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
> + PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
> + PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
> + END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B atfer PMC */
> +static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
> + PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
> + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
> + END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
> + [CFG_PRE_INIT] = exynos7_pre_init_cfg,
> + [CFG_POST_INIT] = exynos7_post_init_cfg,
> + [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
> + [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
> +};
> +
> +static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
> + .cfg = exynos7_ufs_phy_cfgs,
> + .isol = {
> + .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
> + .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
> + .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
> + },
> + .has_symbol_clk = 1,
> +};
> +
> +#endif /* _PHY_EXYNOS7_UFS_H_ */
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> new file mode 100644
> index 000000000000..3077f3901737
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -0,0 +1,359 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * UFS PHY driver for Samsung SoC
> + *
> + * Copyright (C) 2020 Samsung Electronics Co., Ltd.
> + * Author: Seungwon Jeon <[email protected]>
> + * Author: Alim Akhtar <[email protected]>
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define for_each_phy_lane(phy, i) \
> + for (i = 0; i < (phy)->lane_cnt; i++)
> +#define for_each_phy_cfg(cfg) \
> + for (; (cfg)->id; (cfg)++)
> +
> +#define PHY_DEF_LANE_CNT 1
> +
> +static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> + const struct samsung_ufs_phy_cfg *cfg,
> + u8 lane)
> +{
> + enum {LANE_0, LANE_1}; /* lane index */
> +
> + switch (lane) {
> + case LANE_0:
> + writel(cfg->val, (phy)->reg_pma + cfg->off_0);
> + break;
> + case LANE_1:
> + if (cfg->id == PHY_TRSV_BLK)
> + writel(cfg->val, (phy)->reg_pma + cfg->off_1);
> + break;
> + }
> +}
> +
> +static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
> +{
> + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> + const unsigned int timeout_us = 100000;
> + const unsigned int sleep_us = 10;
> + u32 val;
> + int err;
> +
> + err = readl_poll_timeout(
> + ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
> + val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
> + if (err) {
> + dev_err(ufs_phy->dev,
> + "failed to get phy pll lock acquisition %d\n", err);
> + goto out;
> + }
> +
> + err = readl_poll_timeout(
> + ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> + val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
> + if (err)
> + dev_err(ufs_phy->dev,
> + "failed to get phy cdr lock acquisition %d\n", err);
> +out:
> + return err;
> +}
> +
> +static int samsung_ufs_phy_calibrate(struct phy *phy)
> +{
> + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> + struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
> + const struct samsung_ufs_phy_cfg *cfg;
> + int err = 0;
> + int i;
> +
> + if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
> + ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
> + dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
> + return -EINVAL;
> + }
> +
> + cfg = cfgs[ufs_phy->ufs_phy_state];
> + if (!cfg)
> + goto out;
> +
> + for_each_phy_cfg(cfg) {
> + for_each_phy_lane(ufs_phy, i) {
> + samsung_ufs_phy_config(ufs_phy, cfg, i);
> + }
> + }
> +
> + if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
> + err = samsung_ufs_phy_wait_for_lock_acq(phy);
> +
> + /**
> + * In Samsung ufshci, PHY need to be calibrated at different
> + * stages / state mainly before Linkstartup, after Linkstartup,
> + * before power mode change and after power mode change.
> + * Below state machine to make sure to calibrate PHY in each
> + * state. Here after configuring PHY in a given state, will
> + * change the state to next state so that next state phy
> + * calibration value can be programed
> + */
> + switch (ufs_phy->ufs_phy_state) {
> + case CFG_PRE_INIT:
> + ufs_phy->ufs_phy_state = CFG_POST_INIT;
> + break;
> + case CFG_POST_INIT:
> + ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
> + break;
> + case CFG_PRE_PWR_HS:
> + ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
> + break;
> + case CFG_POST_PWR_HS:
> + /* Change back to INIT state */
> + ufs_phy->ufs_phy_state = CFG_PRE_INIT;
> + break;
> + default:
> + dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
> + }
> +
> +out:
> + return err;
> +}
> +
> +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
> +{
> + int ret = 0;
> +
> + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> + if (IS_ERR(phy->tx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx1_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + clk_disable_unprepare(phy->rx0_symbol_clk);
> + }
> +out:
> + return ret;
> +}
> +
> +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
> +{
> + int ret;
> +
> + phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> + if (IS_ERR(phy->ref_clk))
> + dev_err(phy->dev, "failed to get ref_clk clock\n");
> +
> + ret = clk_prepare_enable(phy->ref_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
> + return ret;
> + }
> +
> + dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
> +
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_init(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> + int ret;
> +
> + _phy->lane_cnt = phy->attrs.bus_width;
> + _phy->ufs_phy_state = CFG_PRE_INIT;
> +
> + if (_phy->drvdata->has_symbol_clk) {
> + ret = samsung_ufs_phy_symbol_clk_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy symbol clocks\n");
> + }
> +
> + ret = samsung_ufs_phy_clks_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy clocks\n");
> +
> + samsung_ufs_phy_calibrate(phy);
> +
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_power_on(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> +
> + samsung_ufs_phy_ctrl_isol(_phy, false);
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_power_off(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> +
> + samsung_ufs_phy_ctrl_isol(_phy, true);
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
> + enum phy_mode mode, int submode)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(generic_phy);
> +
> + _phy->mode = PHY_MODE_INVALID;
> +
> + if (mode > 0)
> + _phy->mode = mode;
> +
> + return 0;
> +}
> +
> +static int samsung_ufs_phy_exit(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> +
> + clk_disable_unprepare(_phy->ref_clk);
> +
> + if (_phy->drvdata->has_symbol_clk) {
> + clk_disable_unprepare(_phy->tx0_symbol_clk);
> + clk_disable_unprepare(_phy->rx0_symbol_clk);
> + clk_disable_unprepare(_phy->rx1_symbol_clk);
> + }
> +
> + return 0;
> +}
> +
> +static struct phy_ops samsung_ufs_phy_ops = {
> + .init = samsung_ufs_phy_init,
> + .exit = samsung_ufs_phy_exit,
> + .power_on = samsung_ufs_phy_power_on,
> + .power_off = samsung_ufs_phy_power_off,
> + .calibrate = samsung_ufs_phy_calibrate,
> + .set_mode = samsung_ufs_phy_set_mode,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct of_device_id samsung_ufs_phy_match[];
> +
> +static int samsung_ufs_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + const struct of_device_id *match;
> + struct samsung_ufs_phy *phy;
> + struct phy *gen_phy;
> + struct phy_provider *phy_provider;
> + const struct samsung_ufs_phy_drvdata *drvdata;
> + int err = 0;
> +
> + match = of_match_node(samsung_ufs_phy_match, dev->of_node);
> + if (!match) {
> + err = -EINVAL;
> + dev_err(dev, "failed to get match_node\n");
> + goto out;
> + }
> +
> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> + if (!phy) {
> + err = -ENOMEM;
> + goto out;
> + }
> +
> + phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
> + if (IS_ERR(phy->reg_pma)) {
> + err = PTR_ERR(phy->reg_pma);
> + goto out;
> + }
> +
> + phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> + dev->of_node, "samsung,pmu-syscon");
> + if (IS_ERR(phy->reg_pmu)) {
> + err = PTR_ERR(phy->reg_pmu);
> + dev_err(dev, "failed syscon remap for pmu\n");
> + goto out;
> + }
> +
> + gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
> + if (IS_ERR(gen_phy)) {
> + err = PTR_ERR(gen_phy);
> + dev_err(dev, "failed to create PHY for ufs-phy\n");
> + goto out;
> + }
> +
> + drvdata = match->data;
> + phy->dev = dev;
> + phy->drvdata = drvdata;
> + phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
> + phy->isol = &drvdata->isol;
> + phy->lane_cnt = PHY_DEF_LANE_CNT;
> +
> + phy_set_drvdata(gen_phy, phy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + err = PTR_ERR(phy_provider);
> + dev_err(dev, "failed to register phy-provider\n");
> + goto out;
> + }
> +out:
> + return err;
> +}
> +
> +static const struct of_device_id samsung_ufs_phy_match[] = {
> + {
> + .compatible = "samsung,exynos7-ufs-phy",
> + .data = &exynos7_ufs_phy,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
> +
> +static struct platform_driver samsung_ufs_phy_driver = {
> + .probe = samsung_ufs_phy_probe,
> + .driver = {
> + .name = "samsung-ufs-phy",
> + .of_match_table = samsung_ufs_phy_match,
> + },
> +};
> +module_platform_driver(samsung_ufs_phy_driver);
> +MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
> +MODULE_AUTHOR("Seungwon Jeon <[email protected]>");
> +MODULE_AUTHOR("Alim Akhtar <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
> new file mode 100644
> index 000000000000..5de78710524c
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-samsung-ufs.h
> @@ -0,0 +1,139 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver for Samsung EXYNOS SoC
> + *
> + * Copyright (C) 2020 Samsung Electronics Co., Ltd.
> + * Author: Seungwon Jeon <[email protected]>
> + * Author: Alim Akhtar <[email protected]>
> + *
> + */
> +#ifndef _PHY_SAMSUNG_UFS_
> +#define _PHY_SAMSUNG_UFS_
> +
> +#define PHY_COMN_BLK 1
> +#define PHY_TRSV_BLK 2
> +#define END_UFS_PHY_CFG { 0 }
> +#define PHY_TRSV_CH_OFFSET 0x30
> +#define PHY_APB_ADDR(off) ((off) << 2)
> +
> +#define PHY_COMN_REG_CFG(o, v, d) { \
> + .off_0 = PHY_APB_ADDR((o)), \
> + .off_1 = 0, \
> + .val = (v), \
> + .desc = (d), \
> + .id = PHY_COMN_BLK, \
> +}
> +
> +#define PHY_TRSV_REG_CFG(o, v, d) { \
> + .off_0 = PHY_APB_ADDR((o)), \
> + .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
> + .val = (v), \
> + .desc = (d), \
> + .id = PHY_TRSV_BLK, \
> +}
> +
> +/* UFS PHY registers */
> +#define PHY_PLL_LOCK_STATUS 0x1e
> +#define PHY_CDR_LOCK_STATUS 0x5e
> +
> +#define PHY_PLL_LOCK_BIT BIT(5)
> +#define PHY_CDR_LOCK_BIT BIT(4)
> +
> +/* description for PHY calibration */
> +enum {
> + /* applicable to any */
> + PWR_DESC_ANY = 0,
> + /* mode */
> + PWR_DESC_PWM = 1,
> + PWR_DESC_HS = 2,
> + /* series */
> + PWR_DESC_SER_A = 1,
> + PWR_DESC_SER_B = 2,
> + /* gear */
> + PWR_DESC_G1 = 1,
> + PWR_DESC_G2 = 2,
> + PWR_DESC_G3 = 3,
> + /* field mask */
> + MD_MASK = 0x3,
> + SR_MASK = 0x3,
> + GR_MASK = 0x7,
> +};
> +
> +#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
> +#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
> +#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
> +#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
> +#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
> +#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
> + (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
> +#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_PWM)
> +#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
> + (((s) & SR_MASK) << 2) | PWR_DESC_HS)
> +#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_HS)
> +#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
> + PWR_DESC_ANY, PWR_DESC_ANY)
> +/* PHY calibration point/state */
> +enum {
> + CFG_PRE_INIT,
> + CFG_POST_INIT,
> + CFG_PRE_PWR_HS,
> + CFG_POST_PWR_HS,
> + CFG_TAG_MAX,
> +};
> +
> +struct samsung_ufs_phy_cfg {
> + u32 off_0;
> + u32 off_1;
> + u32 val;
> + u8 desc;
> + u8 id;
> +};
> +
> +struct samsung_ufs_phy_drvdata {
> + const struct samsung_ufs_phy_cfg **cfg;
> + struct pmu_isol {
> + u32 offset;
> + u32 mask;
> + u32 en;
> + } isol;
> + bool has_symbol_clk;
> +};
> +
> +struct samsung_ufs_phy {
> + struct device *dev;
> + void __iomem *reg_pma;
> + struct regmap *reg_pmu;
> + struct clk *ref_clk;
> + struct clk *ref_clk_parent;
> + struct clk *tx0_symbol_clk;
> + struct clk *rx0_symbol_clk;
> + struct clk *rx1_symbol_clk;
> + const struct samsung_ufs_phy_drvdata *drvdata;
> + struct samsung_ufs_phy_cfg **cfg;
> + const struct pmu_isol *isol;
> + u8 lane_cnt;
> + int ufs_phy_state;
> + enum phy_mode mode;
> +};
> +
> +static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
> +{
> + return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
> +}
> +
> +static inline void samsung_ufs_phy_ctrl_isol(
> + struct samsung_ufs_phy *phy, u32 isol)
> +{
> + regmap_update_bits(phy->reg_pmu, phy->isol->offset,
> + phy->isol->mask, isol ? 0 : phy->isol->en);
> +}
> +
> +#include "phy-exynos7-ufs.h"
> +
> +#endif /* _PHY_SAMSUNG_UFS_ */
> --
> 2.17.1
>
--
Regards,
Alim
On 03-07-20, 22:41, Alim Akhtar wrote:
> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> + END_UFS_PHY_CFG
> +};
This is dummy, why not add a check to make config optional?
> +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
> +{
> + int ret = 0;
superfluous init, am sure I flagged it before as well
> +
> + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> + if (IS_ERR(phy->tx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx1_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + clk_disable_unprepare(phy->rx0_symbol_clk);
maybe it will look better if we add common rollback and jump to proper
labels
> +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
> +{
> + int ret;
> +
> + phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> + if (IS_ERR(phy->ref_clk))
> + dev_err(phy->dev, "failed to get ref_clk clock\n");
> +
> + ret = clk_prepare_enable(phy->ref_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
> + return ret;
> + }
> +
> + dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
debug pls
> +static int samsung_ufs_phy_init(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
ss_phy perhaps?
> + int ret;
> +
> + _phy->lane_cnt = phy->attrs.bus_width;
> + _phy->ufs_phy_state = CFG_PRE_INIT;
> +
> + if (_phy->drvdata->has_symbol_clk) {
> + ret = samsung_ufs_phy_symbol_clk_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy symbol clocks\n");
> + }
> +
> + ret = samsung_ufs_phy_clks_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy clocks\n");
> +
> + samsung_ufs_phy_calibrate(phy);
> +
> + return 0;
not return samsung_ufs_phy_calibrate() ?
--
~Vinod
Hi Vinod,
> -----Original Message-----
> From: Vinod Koul <[email protected]>
> Sent: 13 July 2020 11:48
> To: Alim Akhtar <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected]
> Subject: Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for
samsung
> SoC
>
> On 03-07-20, 22:41, Alim Akhtar wrote:
>
> > +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> > + END_UFS_PHY_CFG
> > +};
>
> This is dummy, why not add a check to make config optional?
>
Currently this is dummy, however this might be used for the similar platform
which do some phy tunning post init.
Will just remove this for now for this platform, will add this check in
driver.
> > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > +*phy) {
> > + int ret = 0;
>
> superfluous init, am sure I flagged it before as well
>
Yes, you did, but 0-DAY CI kernel test gave warning [1], so I kept this as
it is.
[1] https://lkml.org/lkml/2020/7/3/81
> > +
> > + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > + if (IS_ERR(phy->tx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > + clk_disable_unprepare(phy->tx0_symbol_clk);
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->rx1_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n",
> __func__, ret);
> > + clk_disable_unprepare(phy->tx0_symbol_clk);
> > + clk_disable_unprepare(phy->rx0_symbol_clk);
>
> maybe it will look better if we add common rollback and jump to proper
labels
>
Sure, will change in next version.
> > +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) {
> > + int ret;
> > +
> > + phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> > + if (IS_ERR(phy->ref_clk))
> > + dev_err(phy->dev, "failed to get ref_clk clock\n");
> > +
> > + ret = clk_prepare_enable(phy->ref_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
__func__,
> ret);
> > + return ret;
> > + }
> > +
> > + dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n",
> > +clk_get_rate(phy->ref_clk));
>
> debug pls
>
Sure, will change
> > +static int samsung_ufs_phy_init(struct phy *phy) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
>
> ss_phy perhaps?
>
Sure, will change
> > + int ret;
> > +
> > + _phy->lane_cnt = phy->attrs.bus_width;
> > + _phy->ufs_phy_state = CFG_PRE_INIT;
> > +
> > + if (_phy->drvdata->has_symbol_clk) {
> > + ret = samsung_ufs_phy_symbol_clk_init(_phy);
> > + if (ret)
> > + dev_err(_phy->dev, "failed to set ufs phy symbol
> clocks\n");
> > + }
> > +
> > + ret = samsung_ufs_phy_clks_init(_phy);
> > + if (ret)
> > + dev_err(_phy->dev, "failed to set ufs phy clocks\n");
> > +
> > + samsung_ufs_phy_calibrate(phy);
> > +
> > + return 0;
>
> not return samsung_ufs_phy_calibrate() ?
> --
Will add an error path.
> ~Vinod
Hi Alim,
On 16-07-20, 06:47, Alim Akhtar wrote:
> > > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > > +*phy) {
> > > + int ret = 0;
> >
> > superfluous init, am sure I flagged it before as well
> >
> Yes, you did, but 0-DAY CI kernel test gave warning [1], so I kept this as
> it is.
> [1] https://lkml.org/lkml/2020/7/3/81
But you moved away from return below to goto, so that is no longer
the case. First use of ret is for clk_prepare_enable() call below which
is not conditional hence this is superfluous. Earlier it was not as it was
conditional so required to be initialized
>
> > > +
> > > + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > > + if (IS_ERR(phy->tx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > > + if (ret) {
> > > + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> > __func__, ret);
> > > + goto out;
> > > + }
--
~Vinod