From: Chen-Yu Tsai <[email protected]>
Hi everyone,
This is v2 of my Allwinner H5 SoC cpufreq support series from way
back [1]. The series enables DVFS for the CPU cores (aka cpufreq)
on the Allwinner H5 SoC. The OPP table was taken from Armbian, with
minor tweaks to the maximum voltage to account for slightly increased
voltage on some of the boards.
In this version, the OPP table and tie in to the CPU cores has been
split out into a separate file, like what was done for the H6. The
patches adding CPU regulator supplies for all the boards that I don't
have have been removed. The series now only enables cpufreq for Libre
Computer ALL-H3-CC and ALL-H5-CC, and Bananapi M2+ v1.2.
For the original Bananapi M2+, if I add the fixed regulator with the
enable pin, it ends up causing some sort of glitch or lock up on the
v1.2, which includes the original dts file. Since I haven't been able
to sort it out yet, I've left it out for now.
Patch 1 assigns the CPU regulator supply to all the CPU cores on the
Libre Computer ALL-H3-CC.
Patch 2 assigns the CPU regulator supply to all the CPU cores on the
Bananapi M2+ v1.2.
Patch 3 fixes the voltages specified for the GPIO-controlled regulator
on the Bananapi M2+ v1.2. The voltages are slightly higher than what
was originally written.
Patch 4 ties the CPU clock to the CPU cores.
Patch 5 adds trip points and cooling maps to the CPU thermal zones.
Patch 6 adds the OPP table, based on the one from Armbian.
Patch 7 hooks up the CPU regulator supply for the Libre Computer
ALL-H3-CC H5 variant, and by extension, the ALL-H5-CC.
Patch 8 hooks up the CPU regulator supply for the Bananapi M2+ v1.2.
Changes since v1:
- Re-ordered patches
- Added patches to set regulator supply for all CPU cores
- Added thermal trip points and cooling maps
- OPP table and assignment split into separate file
- Added patches to tie in OPP table file for the boards I have
Please have a look.
Regards
ChenYu
[1] https://patchwork.kernel.org/cover/10787869/
Chen-Yu Tsai (8):
ARM: dts: sunxi: libretech-all-h3-cc: Add regulator supply to all CPU
cores
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Add regulator supply to all
CPU cores
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
arm64: dts: allwinner: h5: Add clock to CPU cores
arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal
zones
arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
arm64: dts: allwinner: h5: libretech-all-h3-cc: Tie in CPU OPPs
arm64: dts: allwinner: h5: bananapi-m2-plus-v1.2: Tie in CPU OPPs
.../boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 ++++-
.../boot/dts/sunxi-libretech-all-h3-cc.dtsi | 12 +++
.../sun50i-h5-bananapi-m2-plus-v1.2.dts | 1 +
.../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++
.../sun50i-h5-libretech-all-h3-cc.dts | 1 +
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 38 +++++++++
6 files changed, 146 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
--
2.27.0
From: Chen-Yu Tsai <[email protected]>
The Libre Computer ALL-H3-CC H5 variant can work with the standard H5
OPPs. Tie them in to enable CPU frequency scaling.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
index 64d35daf2023..d811df332824 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
#include <arm/sunxi-libretech-all-h3-cc.dtsi>
/ {
--
2.27.0
From: Chen-Yu Tsai <[email protected]>
The device tree currently only assigns the a supply for the first CPU
core, when in reality the regulator supply is shared by all four cores.
This might cause an issue if the implementation does not realize the
sharing of the supply.
Assign the same regulator supply to the remaining CPU cores to address
this.
Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees")
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index 22466afd38a3..a628b5ee72b6 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -28,3 +28,15 @@ reg_vdd_cpux: vdd-cpux {
&cpu0 {
cpu-supply = <®_vdd_cpux>;
};
+
+&cpu1 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <®_vdd_cpux>;
+};
--
2.27.0
From: Chen-Yu Tsai <[email protected]>
The Bananapi M2+ uses a GPIO line to change the effective resistance of
the CPU supply regulator's feedback resistor network. The voltages
described in the device tree were given directly by the vendor. This
turns out to be slightly off compared to the real values.
The updated voltages are based on calculations of the feedback resistor
network, and verified down to three decimal places with a multi-meter.
Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees")
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index a628b5ee72b6..235994a4a2eb 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -16,12 +16,12 @@ reg_vdd_cpux: vdd-cpux {
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1300000>;
+ regulator-min-microvolt = <1108475>;
+ regulator-max-microvolt = <1308475>;
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
gpios-states = <0x1>;
- states = <1100000 0>, <1300000 1>;
+ states = <1108475 0>, <1308475 1>;
};
};
--
2.27.0
From: Chen-Yu Tsai <[email protected]>
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 4462a68c0681..09523f6011c5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -13,6 +13,8 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu1: cpu@1 {
@@ -20,6 +22,8 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu2: cpu@2 {
@@ -27,6 +31,8 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu3: cpu@3 {
@@ -34,6 +40,8 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};
--
2.27.0
On Sat, Jul 18, 2020 at 12:00:45AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <[email protected]>
>
> Hi everyone,
>
> This is v2 of my Allwinner H5 SoC cpufreq support series from way
> back [1]. The series enables DVFS for the CPU cores (aka cpufreq)
> on the Allwinner H5 SoC. The OPP table was taken from Armbian, with
> minor tweaks to the maximum voltage to account for slightly increased
> voltage on some of the boards.
>
> In this version, the OPP table and tie in to the CPU cores has been
> split out into a separate file, like what was done for the H6. The
> patches adding CPU regulator supplies for all the boards that I don't
> have have been removed. The series now only enables cpufreq for Libre
> Computer ALL-H3-CC and ALL-H5-CC, and Bananapi M2+ v1.2.
>
> For the original Bananapi M2+, if I add the fixed regulator with the
> enable pin, it ends up causing some sort of glitch or lock up on the
> v1.2, which includes the original dts file. Since I haven't been able
> to sort it out yet, I've left it out for now.
>
> Patch 1 assigns the CPU regulator supply to all the CPU cores on the
> Libre Computer ALL-H3-CC.
>
> Patch 2 assigns the CPU regulator supply to all the CPU cores on the
> Bananapi M2+ v1.2.
>
> Patch 3 fixes the voltages specified for the GPIO-controlled regulator
> on the Bananapi M2+ v1.2. The voltages are slightly higher than what
> was originally written.
>
> Patch 4 ties the CPU clock to the CPU cores.
>
> Patch 5 adds trip points and cooling maps to the CPU thermal zones.
>
> Patch 6 adds the OPP table, based on the one from Armbian.
>
> Patch 7 hooks up the CPU regulator supply for the Libre Computer
> ALL-H3-CC H5 variant, and by extension, the ALL-H5-CC.
>
> Patch 8 hooks up the CPU regulator supply for the Bananapi M2+ v1.2.
Applied all of them (and fixed the OPP node names in the patch 6)
Maxime