2020-07-22 17:23:37

by Suzuki K Poulose

Subject: [RFC PATCH 07/14] coresight: etm4x: Always read the registers on the host CPU

As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.

Cc: Mathieu Poirier <[email protected]>
Cc: Mike Leach <[email protected]>
Signed-off-by: Suzuki K Poulose <[email protected]>
---
.../coresight/coresight-etm4x-sysfs.c | 23 ++++++++-----------
1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index b673e738bc9a..90c75ba31a0c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2341,23 +2341,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset)
return reg.data;
}

-#define coresight_etm4x_reg(name, offset) \
- coresight_simple_reg32(struct etmv4_drvdata, name, offset)
-
#define coresight_etm4x_cross_read(name, offset) \
coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \
name, offset)

-coresight_etm4x_reg(trcpdcr, TRCPDCR);
-coresight_etm4x_reg(trcpdsr, TRCPDSR);
-coresight_etm4x_reg(trclsr, TRCLSR);
-coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS);
-coresight_etm4x_reg(trcdevid, TRCDEVID);
-coresight_etm4x_reg(trcdevtype, TRCDEVTYPE);
-coresight_etm4x_reg(trcpidr0, TRCPIDR0);
-coresight_etm4x_reg(trcpidr1, TRCPIDR1);
-coresight_etm4x_reg(trcpidr2, TRCPIDR2);
-coresight_etm4x_reg(trcpidr3, TRCPIDR3);
+coresight_etm4x_cross_read(trcpdcr, TRCPDCR);
+coresight_etm4x_cross_read(trcpdsr, TRCPDSR);
+coresight_etm4x_cross_read(trclsr, TRCLSR);
+coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS);
+coresight_etm4x_cross_read(trcdevid, TRCDEVID);
+coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE);
+coresight_etm4x_cross_read(trcpidr0, TRCPIDR0);
+coresight_etm4x_cross_read(trcpidr1, TRCPIDR1);
+coresight_etm4x_cross_read(trcpidr2, TRCPIDR2);
+coresight_etm4x_cross_read(trcpidr3, TRCPIDR3);
coresight_etm4x_cross_read(trcoslsr, TRCOSLSR);
coresight_etm4x_cross_read(trcconfig, TRCCONFIGR);
coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR);
--
2.24.1

2020-07-30 19:57:49

by Mathieu Poirier

Subject: Re: [RFC PATCH 07/14] coresight: etm4x: Always read the registers on the host CPU

On Wed, Jul 22, 2020 at 06:20:33PM +0100, Suzuki K Poulose wrote:
> As we are about to add support for sysreg access to ETM4.4+ components,
> make sure that we read the registers only on the host CPU.
>
> Cc: Mathieu Poirier <[email protected]>
> Cc: Mike Leach <[email protected]>
> Signed-off-by: Suzuki K Poulose <[email protected]>
> ---

Reviewed-by: Mathieu Poirier <[email protected]>

> .../coresight/coresight-etm4x-sysfs.c | 23 ++++++++-----------
> 1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index b673e738bc9a..90c75ba31a0c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2341,23 +2341,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset)
> return reg.data;
> }
>
> -#define coresight_etm4x_reg(name, offset) \
> - coresight_simple_reg32(struct etmv4_drvdata, name, offset)
> -
> #define coresight_etm4x_cross_read(name, offset) \
> coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \
> name, offset)
>
> -coresight_etm4x_reg(trcpdcr, TRCPDCR);
> -coresight_etm4x_reg(trcpdsr, TRCPDSR);
> -coresight_etm4x_reg(trclsr, TRCLSR);
> -coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS);
> -coresight_etm4x_reg(trcdevid, TRCDEVID);
> -coresight_etm4x_reg(trcdevtype, TRCDEVTYPE);
> -coresight_etm4x_reg(trcpidr0, TRCPIDR0);
> -coresight_etm4x_reg(trcpidr1, TRCPIDR1);
> -coresight_etm4x_reg(trcpidr2, TRCPIDR2);
> -coresight_etm4x_reg(trcpidr3, TRCPIDR3);
> +coresight_etm4x_cross_read(trcpdcr, TRCPDCR);
> +coresight_etm4x_cross_read(trcpdsr, TRCPDSR);
> +coresight_etm4x_cross_read(trclsr, TRCLSR);
> +coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS);
> +coresight_etm4x_cross_read(trcdevid, TRCDEVID);
> +coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE);
> +coresight_etm4x_cross_read(trcpidr0, TRCPIDR0);
> +coresight_etm4x_cross_read(trcpidr1, TRCPIDR1);
> +coresight_etm4x_cross_read(trcpidr2, TRCPIDR2);
> +coresight_etm4x_cross_read(trcpidr3, TRCPIDR3);
> coresight_etm4x_cross_read(trcoslsr, TRCOSLSR);
> coresight_etm4x_cross_read(trcconfig, TRCCONFIGR);
> coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR);
> --
> 2.24.1
>