The core interrupt code expects the irq_set_affinity call to update the
effective affinity for the interrupt. This was not being done, so update
iproc_msi_irq_set_affinity() to do so.
Fixes: 3bc2b2348835 ("PCI: iproc: Add iProc PCIe MSI support")
Signed-off-by: Mark Tomlinson <[email protected]>
---
changes in v2:
- Patch 1/2 Added Fixes tag
- Patch 2/2 Replace original change with change suggested by Bjorn
Helgaas.
drivers/pci/controller/pcie-iproc-msi.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c
index 3176ad3ab0e5..908475d27e0e 100644
--- a/drivers/pci/controller/pcie-iproc-msi.c
+++ b/drivers/pci/controller/pcie-iproc-msi.c
@@ -209,15 +209,20 @@ static int iproc_msi_irq_set_affinity(struct irq_data *data,
struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
int target_cpu = cpumask_first(mask);
int curr_cpu;
+ int ret;
curr_cpu = hwirq_to_cpu(msi, data->hwirq);
if (curr_cpu == target_cpu)
- return IRQ_SET_MASK_OK_DONE;
+ ret = IRQ_SET_MASK_OK_DONE;
+ else {
+ /* steer MSI to the target CPU */
+ data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
+ ret = IRQ_SET_MASK_OK;
+ }
- /* steer MSI to the target CPU */
- data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
+ irq_data_update_effective_affinity(data, cpumask_of(target_cpu));
- return IRQ_SET_MASK_OK;
+ return ret;
}
static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
--
2.28.0
For hardware that only supports 32-bit writes to PCI there is the
possibility of clearing RW1C (write-one-to-clear) bits. A rate-limited
messages was introduced by fb2659230120, but rate-limiting is not the
best choice here. Some devices may not show the warnings they should if
another device has just produced a bunch of warnings. Also, the number
of messages can be a nuisance on devices which are otherwise working
fine.
This patch changes the ratelimit to a single warning per bus. This
ensures no bus is 'starved' of emitting a warning and also that there
isn't a continuous stream of warnings. It would be preferable to have a
warning per device, but the pci_dev structure is not available here, and
a lookup from devfn would be far too slow.
Suggested-by: Bjorn Helgaas <[email protected]>
Fixes: fb2659230120 ("PCI: Warn on possible RW1C corruption for sub-32 bit config writes")
Signed-off-by: Mark Tomlinson <[email protected]>
---
drivers/pci/access.c | 9 ++++++---
include/linux/pci.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 79c4a2ef269a..ab85cb7df9b6 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -160,9 +160,12 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
* write happen to have any RW1C (write-one-to-clear) bits set, we
* just inadvertently cleared something we shouldn't have.
*/
- dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
- size, pci_domain_nr(bus), bus->number,
- PCI_SLOT(devfn), PCI_FUNC(devfn), where);
+ if (!bus->unsafe_warn) {
+ dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where);
+ bus->unsafe_warn = true;
+ }
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
tmp = readl(addr) & mask;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 34c1c4f45288..5b6ab593ae09 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -613,6 +613,7 @@ struct pci_bus {
unsigned char primary; /* Number of primary bridge */
unsigned char max_bus_speed; /* enum pci_bus_speed */
unsigned char cur_bus_speed; /* enum pci_bus_speed */
+ bool unsafe_warn; /* warned about RW1C config write */
#ifdef CONFIG_PCI_DOMAINS_GENERIC
int domain_nr;
#endif
--
2.28.0
On Thu, Jul 30, 2020 at 9:40 PM Mark Tomlinson
<[email protected]> wrote:
>
> For hardware that only supports 32-bit writes to PCI there is the
> possibility of clearing RW1C (write-one-to-clear) bits. A rate-limited
> messages was introduced by fb2659230120, but rate-limiting is not the
> best choice here. Some devices may not show the warnings they should if
> another device has just produced a bunch of warnings. Also, the number
> of messages can be a nuisance on devices which are otherwise working
> fine.
>
> This patch changes the ratelimit to a single warning per bus. This
> ensures no bus is 'starved' of emitting a warning and also that there
> isn't a continuous stream of warnings. It would be preferable to have a
> warning per device, but the pci_dev structure is not available here, and
> a lookup from devfn would be far too slow.
If we don't want to just warn when a 8 or 16 bit access occurs (I'm
not sure if 32-bit only accesses is possible or common. Seems like
PCI_COMMAND would always get written?), then a simple way to do this
is just move this out of line and do something like this where the bus
or device is created/registered:
if (bus->ops->write == pci_generic_config_write32)
warn()
>
> Suggested-by: Bjorn Helgaas <[email protected]>
> Fixes: fb2659230120 ("PCI: Warn on possible RW1C corruption for sub-32 bit config writes")
> Signed-off-by: Mark Tomlinson <[email protected]>
> ---
> drivers/pci/access.c | 9 ++++++---
> include/linux/pci.h | 1 +
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/access.c b/drivers/pci/access.c
> index 79c4a2ef269a..ab85cb7df9b6 100644
> --- a/drivers/pci/access.c
> +++ b/drivers/pci/access.c
> @@ -160,9 +160,12 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
> * write happen to have any RW1C (write-one-to-clear) bits set, we
> * just inadvertently cleared something we shouldn't have.
> */
> - dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
> - size, pci_domain_nr(bus), bus->number,
> - PCI_SLOT(devfn), PCI_FUNC(devfn), where);
> + if (!bus->unsafe_warn) {
> + dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
> + size, pci_domain_nr(bus), bus->number,
> + PCI_SLOT(devfn), PCI_FUNC(devfn), where);
> + bus->unsafe_warn = true;
> + }
>
> mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
> tmp = readl(addr) & mask;
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 34c1c4f45288..5b6ab593ae09 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -613,6 +613,7 @@ struct pci_bus {
> unsigned char primary; /* Number of primary bridge */
> unsigned char max_bus_speed; /* enum pci_bus_speed */
> unsigned char cur_bus_speed; /* enum pci_bus_speed */
> + bool unsafe_warn; /* warned about RW1C config write */
Make this a bitfield next to 'is_added'.
> #ifdef CONFIG_PCI_DOMAINS_GENERIC
> int domain_nr;
> #endif
> --
> 2.28.0
>
On Fri, 2020-07-31 at 09:32 -0600, Rob Herring wrote:
>
> If we don't want to just warn when a 8 or 16 bit access occurs (I'm
> not sure if 32-bit only accesses is possible or common. Seems like
> PCI_COMMAND would always get written?), then a simple way to do this
> is just move this out of line and do something like this where the bus
> or device is created/registered:
>
> if (bus->ops->write == pci_generic_config_write32)
> warn()
>
This doesn't work for many of the PCI drivers, since they wrap the call
to pci_generic_config_write32() in their own function.
> >
> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 34c1c4f45288..5b6ab593ae09 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -613,6 +613,7 @@ struct pci_bus {
> > unsigned char primary; /* Number of primary bridge */
> > unsigned char max_bus_speed; /* enum pci_bus_speed */
> > unsigned char cur_bus_speed; /* enum pci_bus_speed */
> > + bool unsafe_warn; /* warned about RW1C config write */
>
> Make this a bitfield next to 'is_added'.
Will do, thanks.