Some platforms may have shared Cause.TI, bailing out in IRQ handler
when clock event is not enabled can give another clock device a chance.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/cevt-r4k.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index f0c52d751d0a..d396b1011fee 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -142,6 +142,15 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
if (handle_perf_irq(r2))
return IRQ_HANDLED;
+ cd = &per_cpu(mips_clockevent_device, cpu);
+ /*
+ * If the clockevent have not enabled, then no need to check the rest.
+ * Some platforms may have shared Cause.TI, bailing out here can
+ * give another clock device a chance.
+ */
+ if (clockevent_state_detached(cd) || clockevent_state_shutdown(cd))
+ return IRQ_NONE;
+
/*
* The same applies to performance counter interrupts. But with the
* above we now know that the reason we got here must be a timer
@@ -150,7 +159,6 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
/* Clear Count/Compare Interrupt */
write_c0_compare(read_c0_compare());
- cd = &per_cpu(mips_clockevent_device, cpu);
cd->event_handler(cd);
return IRQ_HANDLED;
--
2.28.0.rc1