Hi all,
Some Renesas EtherAVB variants support internal clock delay
configuration, which can add larger delays than the delays that are
typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or
"[rt]xc-skew-ps" properties).
Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode. This caused issues with PHY drivers that
implement PHY internal delays properly[1]. Hence a backwards-compatible
workaround was added by masking the PHY mode[2].
This patch series implements the next step of the plan outlined in [3],
and adds proper support for explicit configuration of the MAC internal
clock delays using new "[rt]x-internal-delay-ps" properties. If none of
these properties is present, the driver falls back to the old handling.
This can be considered the MAC counterpart of commit 9150069bf5fc0e86
("dt-bindings: net: Add tx and rx internal delays"), which applies to
the PHY. Note that unlike commit 92252eec913b2dd5 ("net: phy: Add a
helper to return the index for of the internal delay"), no helpers are
provided to parse the DT properties, as so far there is a single user
only, which supports only zero or a single fixed value. Of course such
helpers can be added later, when the need arises, or when deemed useful
otherwise.
This series consists of 4 parts:
1. DT binding updates documenting the new properties, for both the
generic ethernet-controller and the EtherAVB-specific bindings,
=> intended to be merged through net-next.
2. Conversion to json-schema of the Renesas EtherAVB DT bindings.
Technically, the conversion is independent of all of the above.
I included it in this series, as it shows how all sanity checks on
"[rt]x-internal-delay-ps" values are implemented as DT binding
checks.
=> intended to be merged through net-next, or devicetree (ignoring
any conflict due to 1.).
3. EtherAVB driver update implementing support for the new properties.
=> intended to be merged through net-next.
4. DT updates, one for R-Car Gen3 and RZ/G2 SoC families each.
=> intended to be merged through renesas-devel and arm-soc, but
only _after_ 3. has hit upstream.
Changes compared to v2[4]:
- Update recently added board DTS files,
- Add Reviewed-by.
Changes compared to v1[5]:
- Added "[PATCH 1/7] dt-bindings: net: ethernet-controller: Add
internal delay properties",
- Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps",
- Incorporated EtherAVB DT binding conversion to json-schema,
- Add Reviewed-by.
Impacted, tested:
- Salvator-X(S) with R-Car H3 ES1.0 and ES2.0, M3-W, and M3-N.
Not impacted, tested:
- Ebisu with R-Car E3.
Impacted, not tested:
- Salvator-X(S) with other SoC variants,
- ULCB with R-Car H3/M3-W/M3-N variants,
- V3MSK and Eagle with R-Car V3M,
- Draak with R-Car V3H,
- HiHope RZ/G2[MN] with RZ/G2M or RZ/G2N,
- Beacon EmbeddedWorks RZ/G2M Development Kit.
To ease testing, I have pushed this series to the
topic/ravb-internal-clock-delays-v3 branch of my renesas-drivers
repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
Thanks for your comments!
References:
[1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support
for the KSZ9031 PHY")
[2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
delays twice").
https://lore.kernel.org/r/[email protected]/
[3] https://lore.kernel.org/r/CAMuHMdU+MR-2tr3-pH55G0GqPG9HwH3XUd=8HZxprFDMGQeWUw@mail.gmail.com/
[4] https://lore.kernel.org/linux-devicetree/[email protected]/
[5] https://lore.kernel.org/linux-devicetree/[email protected]/
Geert Uytterhoeven (7):
dt-bindings: net: ethernet-controller: Add internal delay properties
dt-bindings: net: renesas,ravb: Document internal clock delay
properties
dt-bindings: net: renesas,etheravb: Convert to json-schema
ravb: Split delay handling in parsing and applying
ravb: Add support for explicit internal clock delay configuration
arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay
handling
arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling
.../bindings/net/ethernet-controller.yaml | 14 +
.../bindings/net/renesas,etheravb.yaml | 261 ++++++++++++++++++
.../devicetree/bindings/net/renesas,ravb.txt | 134 ---------
.../boot/dts/renesas/beacon-renesom-som.dtsi | 3 +-
.../boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +
.../arm64/boot/dts/renesas/r8a77970-eagle.dts | 3 +-
.../arm64/boot/dts/renesas/r8a77970-v3msk.dts | 3 +-
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 +
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 +
.../boot/dts/renesas/salvator-common.dtsi | 2 +-
arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +-
drivers/net/ethernet/renesas/ravb.h | 5 +-
drivers/net/ethernet/renesas/ravb_main.c | 53 +++-
23 files changed, 350 insertions(+), 153 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/renesas,etheravb.yaml
delete mode 100644 Documentation/devicetree/bindings/net/renesas,ravb.txt
--
2.17.1
Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).
Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode. This was wrong, as these are meant solely for the
PHY, not for the MAC. Hence properties were introduced for explicit
configuration of these delays.
Convert the RZ/G2 DTS files from the old to the new scheme:
- Add default "rx-internal-delay-ps" and "tx-internal-delay-ps"
properties to the SoC .dtsi files, to be overridden by board files
where needed,
- Convert board files from "rgmii-*id" PHY modes to "rgmii", adding
the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps"
overrides.
Notes:
- RZ/G2E does not support TX internal delay handling.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
This depends on "[PATCH v3 5/7] ravb: Add support for explicit internal
clock delay configuration", and thus must not be applied before its
dependency has hit upstream.
v3:
- Update new beacon-renesom-som.dtsi and r8a774e1.dtsi,
v2:
- Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps".
---
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 3 ++-
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 ++
6 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index 97272f5fa0abf92e..8ac167aa18f04743 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
@@ -55,7 +55,8 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <1800>;
+ tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index 178401a34cbf8d38..46f1ca0b7ef5e7c2 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -19,7 +19,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
+ tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8e80f50132ad55f5..ed99863f1dd09fd0 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1115,6 +1115,8 @@
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 49e5addcfd97af01..1c76de24d3ea4844 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -989,6 +989,8 @@
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 42171190cce4602d..9fdca4c55ba95608 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -960,6 +960,7 @@
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 0f86cfd524258353..0975bcbc3c502535 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1139,6 +1139,8 @@
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1