From: Hou Zhiqiang <[email protected]>
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 99a386ea691c..2236d3f3089b 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -37,6 +37,10 @@ Required properties:
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
Example:
pcie@3400000 {
--
2.17.1
On Mon, 07 Sep 2020 13:37:57 +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <[email protected]>
>
> This property is to indicate the endianness when accessing the
> PEX_LUT and PF register block, so if these registers are
> implemented in big-endian, specify this property.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
Hi Rob,
Thanks a lot for your review and ack!
Regards,
Zhiqiang
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: 2020??9??15?? 9:31
> To: Z.q. Hou <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; Leo Li <[email protected]>;
> [email protected]; M.h. Lian <[email protected]>;
> [email protected]; [email protected];
> [email protected]; Roy Zang <[email protected]>; Mingkai Hu
> <[email protected]>; [email protected]
> Subject: Re: [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional
> property big-endian
>
> On Mon, 07 Sep 2020 13:37:57 +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <[email protected]>
> >
> > This property is to indicate the endianness when accessing the PEX_LUT
> > and PF register block, so if these registers are implemented in
> > big-endian, specify this property.
> >
> > Signed-off-by: Hou Zhiqiang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
>
> Acked-by: Rob Herring <[email protected]>