This patch series adds support for the external interrupt controller
(SIRQ) found in the Actions Semi Owl family of SoC's (S500, S700 and
S900). The controller handles up to 3 external interrupt lines through
dedicated SIRQ pins.
This is a rework of the patch series submitted some time ago by
Parthiban Nallathambi:
https://lore.kernel.org/lkml/[email protected]/
Please note I have dropped, for the moment, the S700 related patches
since I do not own a compatible hardware for testing. I'm using instead
an S500 SoC based board for which I have already provided the initial
support:
https://lore.kernel.org/lkml/[email protected]/
Additionally, I have taken the authorship for the driver patch,
considering the original code has been already modified to a great
extent and I'm firmly committed to maintaining it in the long run.
The SIRQ controller support is a prerequisite of the upcoming MFD
driver for the Actions Semi ATC260x PMICs.
Thanks and regards,
Cristi
Changes in v6:
- Integrated binding doc related feedback from Rob and Marc
- Updated cover letter to handle the authorship issue indicated by Mani
- Rebased patch series on v5.9-rc4
Changes in v5:
- Integrated Marc's review (more details in the driver patch changelog)
- Rebased patch series on v5.9-rc1
Changes in v4:
- Simplified the DTS structure:
* dropped 'actions,sirq-shared-reg' node, now the differentiation
between SoC variants is handled via the compatible property
* dropped 'actions,sirq-reg-offset', now controller base address in
DTS points to SIRQ0 register, so no additional information is
required for S500 and S700, while for S900 SoC the offsets of SIRQ1
and SIRQ2 regs are provided by the driver
* 'actions,ext-irq-range' was replaced with 'actions,ext-interrupts',
an array of the GIC interrupts triggered by the controller
- Fixed wrong INTC_EXTCTL_TYPE_MASK definition
- Removed redundant irq_fwspec checks in owl_sirq_domain_alloc()
- Improved error handling in owl_sirq_of_init()
- Added yaml binding document
- Dropped S700 related DTS patches for lack of testing hardware:
* arm64: dts: actions: Add sirq node for Actions Semi S700
* arm64: dts: actions: s700-cubieboard7: Enable SIRQ
- Updated MAINTAINERS
- Rebased patchset on kernel v5.8
- Cosmetic changes
* Ordered include statements alphabetically
* Added comment to owl_sirq_set_type() describing conversion of falling
edge or active low signals
* Replaced IRQF_TRIGGER_* with corresponding IRQ_TYPE_* variants
* Ensured data types and function naming are consistent regarding the
'owl_sirq' prefix
Changes in v3 (Parthiban Nallathambi):
- Set default operating frequency to 24MHz
- Falling edge and Low Level interrupts translated to rising edge and high level
- Introduced common function with lock handling for register read and write
- Used direct GIC interrupt number for interrupt local hwirq and finding offset
using DT entry (range) when registers are shared
- Changed irq_ack to irq_eoi
- Added translation method for irq_domain_ops
- Clearing interrupt pending based on bitmask for edge triggered
- Added pinctrl definition for sirq for cubieboard7. This depends on,
https://lore.kernel.org/patchwork/patch/1012859/
Changes in v2 (Parthiban Nallathambi):
- Added SIRQ as hierarchical chip
GIC <----> SIRQ <----> External interrupt controller/Child devices
- Device binding updates with vendor prefix
- Register sharing handled globally and common init sequence/data for all
actions SoC family
Cristian Ciocaltea (3):
dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
irqchip: Add Actions Semi Owl SIRQ controller
MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller
.../actions,owl-sirq.yaml | 65 ++++
MAINTAINERS | 2 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-owl-sirq.c | 359 ++++++++++++++++++
4 files changed, 427 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
create mode 100644 drivers/irqchip/irq-owl-sirq.c
--
2.28.0
Add entries for Actions Semi Owl SIRQ controller binding and driver.
Signed-off-by: Cristian Ciocaltea <[email protected]>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9544eec4eff2..04c75815fac6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1525,6 +1525,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
F: Documentation/devicetree/bindings/dma/owl-dma.txt
F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
+F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
F: Documentation/devicetree/bindings/pinctrl/actions,*
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
@@ -1536,6 +1537,7 @@ F: drivers/clk/actions/
F: drivers/clocksource/timer-owl*
F: drivers/dma/owl-dma.c
F: drivers/i2c/busses/i2c-owl.c
+F: drivers/irqchip/irq-owl-sirq.c
F: drivers/mmc/host/owl-mmc.c
F: drivers/pinctrl/actions/*
F: drivers/soc/actions/
--
2.28.0
This interrupt controller is found in the Actions Semi Owl SoCs (S500,
S700 and S900) and provides support for handling up to 3 external
interrupt lines.
Each line can be independently configured as interrupt and triggers on
either of the edges or either of the levels. Additionally, each line
can also be masked individually.
The patch is based on the work started by Parthiban Nallathambi:
https://lore.kernel.org/lkml/[email protected]/
Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
[cristi: optimized DT, various fixes/cleanups/improvements]
Signed-off-by: Cristian Ciocaltea <[email protected]>
---
Changes in v6:
- Got rid of the of_match table and used IRQCHIP_DECLARE for each
of the 3 driver compatibles
- Transformed owl_sirq_of_init() into a helper function: renamed
to owl_sirq_of_init(), dropped handling of the custom property
'actions,ext-interrupts' and used standard API for parsing the
replacement 'interrupts'
- Used GIC_SPI constant instead of the related number
- Minor changes in the commit message
Changes in v5 - according to Marc's review:
- Updated commit message
- Aligned members in struct owl_sirq_chip_data
- Added naming for SIRQ0 control register offset
- Improved code readability by using FIELD_PREP and FIELD_GET
- Dropped redundant handling of the IRQ trigger information
- Added missing irq_set_affinity to owl_sirq_chip descriptor
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-owl-sirq.c | 359 +++++++++++++++++++++++++++++++++
2 files changed, 360 insertions(+)
create mode 100644 drivers/irqchip/irq-owl-sirq.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 133f9c45744a..b8eb5b8b766d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
+obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
obj-$(CONFIG_EXYNOS_IRQ_COMBINER) += exynos-combiner.o
diff --git a/drivers/irqchip/irq-owl-sirq.c b/drivers/irqchip/irq-owl-sirq.c
new file mode 100644
index 000000000000..6e4127465094
--- /dev/null
+++ b/drivers/irqchip/irq-owl-sirq.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi Owl SoCs SIRQ interrupt controller driver
+ *
+ * Copyright (C) 2014 Actions Semi Inc.
+ * David Liu <[email protected]>
+ *
+ * Author: Parthiban Nallathambi <[email protected]>
+ * Author: Saravanan Sekar <[email protected]>
+ * Author: Cristian Ciocaltea <[email protected]>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define NUM_SIRQ 3
+
+#define INTC_EXTCTL_PENDING BIT(0)
+#define INTC_EXTCTL_CLK_SEL BIT(4)
+#define INTC_EXTCTL_EN BIT(5)
+#define INTC_EXTCTL_TYPE_MASK GENMASK(7, 6)
+#define INTC_EXTCTL_TYPE_HIGH 0
+#define INTC_EXTCTL_TYPE_LOW BIT(6)
+#define INTC_EXTCTL_TYPE_RISING BIT(7)
+#define INTC_EXTCTL_TYPE_FALLING (BIT(6) | BIT(7))
+
+/* S500 & S700 SIRQ control register masks */
+#define INTC_EXTCTL_SIRQ0_MASK GENMASK(23, 16)
+#define INTC_EXTCTL_SIRQ1_MASK GENMASK(15, 8)
+#define INTC_EXTCTL_SIRQ2_MASK GENMASK(7, 0)
+
+/* S900 SIRQ control register offsets, relative to controller base address */
+#define INTC_EXTCTL0 0x0000
+#define INTC_EXTCTL1 0x0328
+#define INTC_EXTCTL2 0x032c
+
+struct owl_sirq_params {
+ /* INTC_EXTCTL reg shared for all three SIRQ lines */
+ bool reg_shared;
+ /* INTC_EXTCTL reg offsets relative to controller base address */
+ u16 reg_offset[NUM_SIRQ];
+};
+
+struct owl_sirq_chip_data {
+ const struct owl_sirq_params *params;
+ void __iomem *base;
+ raw_spinlock_t lock;
+ u32 ext_irqs[NUM_SIRQ];
+};
+
+/* S500 & S700 SoCs */
+static const struct owl_sirq_params owl_sirq_s500_params = {
+ .reg_shared = true,
+ .reg_offset = { 0, 0, 0 },
+};
+
+/* S900 SoC */
+static const struct owl_sirq_params owl_sirq_s900_params = {
+ .reg_shared = false,
+ .reg_offset = { INTC_EXTCTL0, INTC_EXTCTL1, INTC_EXTCTL2 },
+};
+
+static u32 owl_field_get(u32 val, u32 index)
+{
+ switch (index) {
+ case 0:
+ return FIELD_GET(INTC_EXTCTL_SIRQ0_MASK, val);
+ case 1:
+ return FIELD_GET(INTC_EXTCTL_SIRQ1_MASK, val);
+ case 2:
+ default:
+ return FIELD_GET(INTC_EXTCTL_SIRQ2_MASK, val);
+ }
+}
+
+static u32 owl_field_prep(u32 val, u32 index)
+{
+ switch (index) {
+ case 0:
+ return FIELD_PREP(INTC_EXTCTL_SIRQ0_MASK, val);
+ case 1:
+ return FIELD_PREP(INTC_EXTCTL_SIRQ1_MASK, val);
+ case 2:
+ default:
+ return FIELD_PREP(INTC_EXTCTL_SIRQ2_MASK, val);
+ }
+}
+
+static u32 owl_sirq_read_extctl(struct owl_sirq_chip_data *data, u32 index)
+{
+ u32 val;
+
+ val = readl_relaxed(data->base + data->params->reg_offset[index]);
+ if (data->params->reg_shared)
+ val = owl_field_get(val, index);
+
+ return val;
+}
+
+static void owl_sirq_write_extctl(struct owl_sirq_chip_data *data,
+ u32 extctl, u32 index)
+{
+ u32 val;
+
+ if (data->params->reg_shared) {
+ val = readl_relaxed(data->base + data->params->reg_offset[index]);
+ val &= ~owl_field_prep(0xff, index);
+ extctl = owl_field_prep(extctl, index) | val;
+ }
+
+ writel_relaxed(extctl, data->base + data->params->reg_offset[index]);
+}
+
+static void owl_sirq_clear_set_extctl(struct owl_sirq_chip_data *d,
+ u32 clear, u32 set, u32 index)
+{
+ unsigned long flags;
+ u32 val;
+
+ raw_spin_lock_irqsave(&d->lock, flags);
+ val = owl_sirq_read_extctl(d, index);
+ val &= ~clear;
+ val |= set;
+ owl_sirq_write_extctl(d, val, index);
+ raw_spin_unlock_irqrestore(&d->lock, flags);
+}
+
+static void owl_sirq_eoi(struct irq_data *data)
+{
+ struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data);
+
+ /*
+ * Software must clear external interrupt pending, when interrupt type
+ * is edge triggered, so we need per SIRQ based clearing.
+ */
+ if (!irqd_is_level_type(data))
+ owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_PENDING,
+ data->hwirq);
+
+ irq_chip_eoi_parent(data);
+}
+
+static void owl_sirq_mask(struct irq_data *data)
+{
+ struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data);
+
+ owl_sirq_clear_set_extctl(chip_data, INTC_EXTCTL_EN, 0, data->hwirq);
+ irq_chip_mask_parent(data);
+}
+
+static void owl_sirq_unmask(struct irq_data *data)
+{
+ struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data);
+
+ owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_EN, data->hwirq);
+ irq_chip_unmask_parent(data);
+}
+
+/*
+ * GIC does not handle falling edge or active low, hence SIRQ shall be
+ * programmed to convert falling edge to rising edge signal and active
+ * low to active high signal.
+ */
+static int owl_sirq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data);
+ u32 sirq_type;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_LOW:
+ sirq_type = INTC_EXTCTL_TYPE_LOW;
+ type = IRQ_TYPE_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ sirq_type = INTC_EXTCTL_TYPE_HIGH;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ sirq_type = INTC_EXTCTL_TYPE_FALLING;
+ type = IRQ_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ sirq_type = INTC_EXTCTL_TYPE_RISING;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ owl_sirq_clear_set_extctl(chip_data, INTC_EXTCTL_TYPE_MASK, sirq_type,
+ data->hwirq);
+
+ return irq_chip_set_type_parent(data, type);
+}
+
+static struct irq_chip owl_sirq_chip = {
+ .name = "owl-sirq",
+ .irq_mask = owl_sirq_mask,
+ .irq_unmask = owl_sirq_unmask,
+ .irq_eoi = owl_sirq_eoi,
+ .irq_set_type = owl_sirq_set_type,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+#endif
+};
+
+static int owl_sirq_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (!is_of_node(fwspec->fwnode))
+ return -EINVAL;
+
+ if (fwspec->param_count != 2 || fwspec->param[0] >= NUM_SIRQ)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[0];
+ *type = fwspec->param[1];
+
+ return 0;
+}
+
+static int owl_sirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct owl_sirq_chip_data *chip_data = domain->host_data;
+ struct irq_fwspec *fwspec = data;
+ struct irq_fwspec parent_fwspec;
+ irq_hw_number_t hwirq;
+ unsigned int type;
+ int ret;
+
+ if (WARN_ON(nr_irqs != 1))
+ return -EINVAL;
+
+ ret = owl_sirq_domain_translate(domain, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_LEVEL_HIGH:
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ type = IRQ_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ type = IRQ_TYPE_LEVEL_HIGH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &owl_sirq_chip,
+ chip_data);
+
+ parent_fwspec.fwnode = domain->parent->fwnode;
+ parent_fwspec.param_count = 3;
+ parent_fwspec.param[0] = GIC_SPI;
+ parent_fwspec.param[1] = chip_data->ext_irqs[hwirq];
+ parent_fwspec.param[2] = type;
+
+ return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
+}
+
+static const struct irq_domain_ops owl_sirq_domain_ops = {
+ .translate = owl_sirq_domain_translate,
+ .alloc = owl_sirq_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int __init owl_sirq_init(const struct owl_sirq_params *params,
+ struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *parent_domain;
+ struct owl_sirq_chip_data *chip_data;
+ int ret, i;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("%pOF: failed to find sirq parent domain\n", node);
+ return -ENXIO;
+ }
+
+ chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
+ if (!chip_data)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&chip_data->lock);
+
+ chip_data->params = params;
+
+ chip_data->base = of_iomap(node, 0);
+ if (!chip_data->base) {
+ pr_err("%pOF: failed to map sirq registers\n", node);
+ ret = -ENXIO;
+ goto out_free;
+ }
+
+ for (i = 0; i < NUM_SIRQ; i++) {
+ struct of_phandle_args irq;
+
+ ret = of_irq_parse_one(node, i, &irq);
+ if (ret) {
+ pr_err("%pOF: failed to parse interrupt %d\n", node, i);
+ goto out_unmap;
+ }
+
+ if (WARN_ON(irq.args_count != 3)) {
+ ret = -EINVAL;
+ goto out_unmap;
+ }
+
+ chip_data->ext_irqs[i] = irq.args[1];
+
+ /* Set 24MHz external interrupt clock freq */
+ owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_CLK_SEL, i);
+ }
+
+ domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_SIRQ, node,
+ &owl_sirq_domain_ops, chip_data);
+ if (!domain) {
+ pr_err("%pOF: failed to add domain\n", node);
+ ret = -ENOMEM;
+ goto out_unmap;
+ }
+
+ return 0;
+
+out_unmap:
+ iounmap(chip_data->base);
+out_free:
+ kfree(chip_data);
+
+ return ret;
+}
+
+static int __init owl_sirq_s500_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return owl_sirq_init(&owl_sirq_s500_params, node, parent);
+}
+
+IRQCHIP_DECLARE(owl_sirq_s500, "actions,s500-sirq", owl_sirq_s500_of_init);
+IRQCHIP_DECLARE(owl_sirq_s700, "actions,s700-sirq", owl_sirq_s500_of_init);
+
+static int __init owl_sirq_s900_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return owl_sirq_init(&owl_sirq_s900_params, node, parent);
+}
+
+IRQCHIP_DECLARE(owl_sirq_s900, "actions,s900-sirq", owl_sirq_s900_of_init);
--
2.28.0
On 2020-09-08 09:20, Cristian Ciocaltea wrote:
> This interrupt controller is found in the Actions Semi Owl SoCs (S500,
> S700 and S900) and provides support for handling up to 3 external
> interrupt lines.
>
> Each line can be independently configured as interrupt and triggers on
> either of the edges or either of the levels. Additionally, each line
> can also be masked individually.
>
> The patch is based on the work started by Parthiban Nallathambi:
> https://lore.kernel.org/lkml/[email protected]/
>
> Signed-off-by: Parthiban Nallathambi <[email protected]>
> Signed-off-by: Saravanan Sekar <[email protected]>
> [cristi: optimized DT, various fixes/cleanups/improvements]
> Signed-off-by: Cristian Ciocaltea <[email protected]>
Who is the author of these patches? If this is a co-development, please
use the relevant tags. Otherwise, the author of the patch must come as
the first SoB.
The patch itself looks good.
M.
--
Jazz is not dead. It just smells funny...
Hi Marc,
On Fri, Sep 11, 2020 at 05:22:41PM +0100, Marc Zyngier wrote:
> On 2020-09-08 09:20, Cristian Ciocaltea wrote:
> > This interrupt controller is found in the Actions Semi Owl SoCs (S500,
> > S700 and S900) and provides support for handling up to 3 external
> > interrupt lines.
> >
> > Each line can be independently configured as interrupt and triggers on
> > either of the edges or either of the levels. Additionally, each line
> > can also be masked individually.
> >
> > The patch is based on the work started by Parthiban Nallathambi:
> > https://lore.kernel.org/lkml/[email protected]/
> >
> > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > Signed-off-by: Saravanan Sekar <[email protected]>
> > [cristi: optimized DT, various fixes/cleanups/improvements]
> > Signed-off-by: Cristian Ciocaltea <[email protected]>
>
> Who is the author of these patches? If this is a co-development, please
> use the relevant tags. Otherwise, the author of the patch must come as
> the first SoB.
I took the authorship for the driver patch, as mentioned in the cover
letter. So, if I understand correctly, my SoB should be moved on top and
I assume I also need to drop the related comment line.
> The patch itself looks good.
Thanks for reviewing,
Cristi
>
> M.
> --
> Jazz is not dead. It just smells funny...
Cristian,
On 2020-09-14 08:02, Cristian Ciocaltea wrote:
> Hi Marc,
>
> On Fri, Sep 11, 2020 at 05:22:41PM +0100, Marc Zyngier wrote:
>> On 2020-09-08 09:20, Cristian Ciocaltea wrote:
>> > This interrupt controller is found in the Actions Semi Owl SoCs (S500,
>> > S700 and S900) and provides support for handling up to 3 external
>> > interrupt lines.
>> >
>> > Each line can be independently configured as interrupt and triggers on
>> > either of the edges or either of the levels. Additionally, each line
>> > can also be masked individually.
>> >
>> > The patch is based on the work started by Parthiban Nallathambi:
>> > https://lore.kernel.org/lkml/[email protected]/
>> >
>> > Signed-off-by: Parthiban Nallathambi <[email protected]>
>> > Signed-off-by: Saravanan Sekar <[email protected]>
>> > [cristi: optimized DT, various fixes/cleanups/improvements]
>> > Signed-off-by: Cristian Ciocaltea <[email protected]>
>>
>> Who is the author of these patches? If this is a co-development,
>> please
>> use the relevant tags. Otherwise, the author of the patch must come as
>> the first SoB.
>
> I took the authorship for the driver patch, as mentioned in the cover
> letter. So, if I understand correctly, my SoB should be moved on top
> and
> I assume I also need to drop the related comment line.
Not quite. Please look at Documentation/process/submitting-patches.rst.
If Parthiban and Saravanan haven't authored anything in this patch,
then drop them from the SoB list. If they have contributed to the
patch (which I expect), then their SoB must be preceded by their own
Co-developed-by: tag. To sum it up, it probably should look like:
Co-developed-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Parthiban Nallathambi <[email protected]>
Co-developed-by: Saravanan Sekar <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
This is of course an assumption, and you should check it with the
individuals above.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On Mon, Sep 14, 2020 at 09:07:18AM +0100, Marc Zyngier wrote:
> Cristian,
>
> On 2020-09-14 08:02, Cristian Ciocaltea wrote:
> > Hi Marc,
> >
> > On Fri, Sep 11, 2020 at 05:22:41PM +0100, Marc Zyngier wrote:
> > > On 2020-09-08 09:20, Cristian Ciocaltea wrote:
> > > > This interrupt controller is found in the Actions Semi Owl SoCs (S500,
> > > > S700 and S900) and provides support for handling up to 3 external
> > > > interrupt lines.
> > > >
> > > > Each line can be independently configured as interrupt and triggers on
> > > > either of the edges or either of the levels. Additionally, each line
> > > > can also be masked individually.
> > > >
> > > > The patch is based on the work started by Parthiban Nallathambi:
> > > > https://lore.kernel.org/lkml/[email protected]/
> > > >
> > > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > > [cristi: optimized DT, various fixes/cleanups/improvements]
> > > > Signed-off-by: Cristian Ciocaltea <[email protected]>
> > >
> > > Who is the author of these patches? If this is a co-development,
> > > please
> > > use the relevant tags. Otherwise, the author of the patch must come as
> > > the first SoB.
> >
> > I took the authorship for the driver patch, as mentioned in the cover
> > letter. So, if I understand correctly, my SoB should be moved on top and
> > I assume I also need to drop the related comment line.
>
> Not quite. Please look at Documentation/process/submitting-patches.rst.
Yes, I have read it, but most probably I missed the information that
clarifies this authorship change handling.
> If Parthiban and Saravanan haven't authored anything in this patch,
> then drop them from the SoB list.
Sorry I haven't properly explained this before!
Their contributions to the driver code stopped in 2018, when v3 of the
patch series has been submitted.
> If they have contributed to the
> patch (which I expect), then their SoB must be preceded by their own
> Co-developed-by: tag.
Starting with v4, the work has been done exclusively by myself.
> To sum it up, it probably should look like:
>
> Co-developed-by: Parthiban Nallathambi <[email protected]>
> Signed-off-by: Parthiban Nallathambi <[email protected]>
> Co-developed-by: Saravanan Sekar <[email protected]>
> Signed-off-by: Saravanan Sekar <[email protected]>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
>
> This is of course an assumption, and you should check it with the
> individuals above.
I have recently contacted Parthiban and he agreed that I can take the
authorship. So I should proceed with the 1st approach?
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
Thanks,
Cristi
On 2020-09-14 09:51, Cristian Ciocaltea wrote:
> On Mon, Sep 14, 2020 at 09:07:18AM +0100, Marc Zyngier wrote:
>> Cristian,
>>
>> On 2020-09-14 08:02, Cristian Ciocaltea wrote:
>> > Hi Marc,
>> >
>> > On Fri, Sep 11, 2020 at 05:22:41PM +0100, Marc Zyngier wrote:
>> > > On 2020-09-08 09:20, Cristian Ciocaltea wrote:
>> > > > This interrupt controller is found in the Actions Semi Owl SoCs (S500,
>> > > > S700 and S900) and provides support for handling up to 3 external
>> > > > interrupt lines.
>> > > >
>> > > > Each line can be independently configured as interrupt and triggers on
>> > > > either of the edges or either of the levels. Additionally, each line
>> > > > can also be masked individually.
>> > > >
>> > > > The patch is based on the work started by Parthiban Nallathambi:
>> > > > https://lore.kernel.org/lkml/[email protected]/
>> > > >
>> > > > Signed-off-by: Parthiban Nallathambi <[email protected]>
>> > > > Signed-off-by: Saravanan Sekar <[email protected]>
>> > > > [cristi: optimized DT, various fixes/cleanups/improvements]
>> > > > Signed-off-by: Cristian Ciocaltea <[email protected]>
>> > >
>> > > Who is the author of these patches? If this is a co-development,
>> > > please
>> > > use the relevant tags. Otherwise, the author of the patch must come as
>> > > the first SoB.
>> >
>> > I took the authorship for the driver patch, as mentioned in the cover
>> > letter. So, if I understand correctly, my SoB should be moved on top and
>> > I assume I also need to drop the related comment line.
>>
>> Not quite. Please look at
>> Documentation/process/submitting-patches.rst.
>
> Yes, I have read it, but most probably I missed the information that
> clarifies this authorship change handling.
>
>> If Parthiban and Saravanan haven't authored anything in this patch,
>> then drop them from the SoB list.
>
> Sorry I haven't properly explained this before!
>
> Their contributions to the driver code stopped in 2018, when v3 of the
> patch series has been submitted.
>
>> If they have contributed to the
>> patch (which I expect), then their SoB must be preceded by their own
>> Co-developed-by: tag.
>
> Starting with v4, the work has been done exclusively by myself.
>
>> To sum it up, it probably should look like:
>>
>> Co-developed-by: Parthiban Nallathambi <[email protected]>
>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>> Co-developed-by: Saravanan Sekar <[email protected]>
>> Signed-off-by: Saravanan Sekar <[email protected]>
>> Signed-off-by: Cristian Ciocaltea <[email protected]>
>>
>> This is of course an assumption, and you should check it with the
>> individuals above.
>
> I have recently contacted Parthiban and he agreed that I can take the
> authorship. So I should proceed with the 1st approach?
The authorship of the patch is one thing, acknowledging the work done
by others is another. As you said above, you started by contributing to
an existing series, instead of writing it from scratch. You changed it
to a degree where it makes sense for you to be the author of the
patches,
but it doesn't invalidate the contributions made by others before you.
Unless the two other contributors explicitly say they'd rather not be
named, I don't see how you can avoid mentioning them.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On Mon, Sep 14, 2020 at 10:19:31AM +0100, Marc Zyngier wrote:
> On 2020-09-14 09:51, Cristian Ciocaltea wrote:
> > On Mon, Sep 14, 2020 at 09:07:18AM +0100, Marc Zyngier wrote:
> > > Cristian,
> > >
> > > On 2020-09-14 08:02, Cristian Ciocaltea wrote:
> > > > Hi Marc,
> > > >
> > > > On Fri, Sep 11, 2020 at 05:22:41PM +0100, Marc Zyngier wrote:
> > > > > On 2020-09-08 09:20, Cristian Ciocaltea wrote:
> > > > > > This interrupt controller is found in the Actions Semi Owl SoCs (S500,
> > > > > > S700 and S900) and provides support for handling up to 3 external
> > > > > > interrupt lines.
> > > > > >
> > > > > > Each line can be independently configured as interrupt and triggers on
> > > > > > either of the edges or either of the levels. Additionally, each line
> > > > > > can also be masked individually.
> > > > > >
> > > > > > The patch is based on the work started by Parthiban Nallathambi:
> > > > > > https://lore.kernel.org/lkml/[email protected]/
> > > > > >
> > > > > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > > > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > > > > [cristi: optimized DT, various fixes/cleanups/improvements]
> > > > > > Signed-off-by: Cristian Ciocaltea <[email protected]>
> > > > >
> > > > > Who is the author of these patches? If this is a co-development,
> > > > > please
> > > > > use the relevant tags. Otherwise, the author of the patch must come as
> > > > > the first SoB.
> > > >
> > > > I took the authorship for the driver patch, as mentioned in the cover
> > > > letter. So, if I understand correctly, my SoB should be moved on top and
> > > > I assume I also need to drop the related comment line.
> > >
> > > Not quite. Please look at
> > > Documentation/process/submitting-patches.rst.
> >
> > Yes, I have read it, but most probably I missed the information that
> > clarifies this authorship change handling.
> >
> > > If Parthiban and Saravanan haven't authored anything in this patch,
> > > then drop them from the SoB list.
> >
> > Sorry I haven't properly explained this before!
> >
> > Their contributions to the driver code stopped in 2018, when v3 of the
> > patch series has been submitted.
> >
> > > If they have contributed to the
> > > patch (which I expect), then their SoB must be preceded by their own
> > > Co-developed-by: tag.
> >
> > Starting with v4, the work has been done exclusively by myself.
> >
> > > To sum it up, it probably should look like:
> > >
> > > Co-developed-by: Parthiban Nallathambi <[email protected]>
> > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > Co-developed-by: Saravanan Sekar <[email protected]>
> > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > Signed-off-by: Cristian Ciocaltea <[email protected]>
> > >
> > > This is of course an assumption, and you should check it with the
> > > individuals above.
> >
> > I have recently contacted Parthiban and he agreed that I can take the
> > authorship. So I should proceed with the 1st approach?
>
> The authorship of the patch is one thing, acknowledging the work done
> by others is another. As you said above, you started by contributing to
> an existing series, instead of writing it from scratch. You changed it
> to a degree where it makes sense for you to be the author of the patches,
> but it doesn't invalidate the contributions made by others before you.
>
> Unless the two other contributors explicitly say they'd rather not be
> named, I don't see how you can avoid mentioning them.
I just want to do the right thing and follow the recommended procedure.
That's why I initially kept all the SoBs, but obviously I still missed
some bits and pieces, as you have pointed out.
So I will add the indicated Co-developed-by tags and resend the series.
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
Thanks a lot for all the clarifications,
Cristi