This series make it possible to use more HDMI modes on RK3328,
and presumably also on RK3228. It also prepares for a future YUV420 and
10-bit output series.
Part of this has been reworked from vendor BSP 4.4 kernel commits.
Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver.
Patch 6 prepares for use of high TMDS bit rates used with HDMI 2.0 and
10-bit output modes.
Patch 7-13 changes rk3228/rk3328 to use mode_valid functions suited for
the inno hdmi phy instead of the dw-hdmi phy. These changes allows for
more CEA modes to be usable, e.g. some 4K and fractal modes.
Patch 14 adds support for more pixel clock rates in order to support
common DMT modes in addition to CEA modes.
Note: I have only been able to build test RK322x related changes
as I do not have any RK322x device to test on.
All modes, including fractal modes, has been tested with modetest on
a RK3328 Rock64 device using e.g.
modetest -M rockchip -s 39:3840x2160-29.97
Changes in v2:
- collect acked-by tag
- drop the limit resolution width to 3840 patch
This series is also available at [1] and the early work on YUV420 and
10-bit output is available at [2].
[1] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-inno-hdmi-phy
[2] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-bus-format
Regards,
Jonas
Algea Cao (1):
phy/rockchip: inno-hdmi: Support more pre-pll configuration
Huicong Xu (1):
phy/rockchip: inno-hdmi: force set_rate on power_on
Jonas Karlman (11):
phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328
phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate
phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write
drm/rockchip: dw-hdmi: allow high tmds bit rates
drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328
clk: rockchip: set parent rate for DCLK_VOP clock on rk3228
arm64: dts: rockchip: increase vop clock rate on rk3328
arm64: dts: rockchip: add vpll clock to hdmi node on rk3328
ARM: dts: rockchip: add vpll clock to hdmi node on rk3228
drm/rockchip: dw-hdmi: limit tmds to 340mhz on rk3228/rk3328
drm/rockchip: dw-hdmi: remove unused plat_data on rk3228/rk3328
Zheng Yang (1):
phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate
arch/arm/boot/dts/rk322x.dtsi | 4 +-
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +-
drivers/clk/rockchip/clk-rk3228.c | 2 +-
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 47 ++++++--
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------
5 files changed, 120 insertions(+), 49 deletions(-)
--
2.17.1
From: Zheng Yang <[email protected]>
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found
in the pre pll config table when the fractal divider is used.
This can prevent proper power_on because a tmdsclock for the new rate
is not found in the pre pll config table.
Fix this by saving and returning a rounded pixel rate that exist
in the pre pll config table.
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
Signed-off-by: Zheng Yang <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index b0ac1d3ee390..093d2334e8cd 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
}
- inno->pixclock = vco;
- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
+ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
- return vco;
+ dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
+ __func__, inno->pixclock, vco);
+
+ return inno->pixclock;
}
static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
--
2.17.1
On 09/01/20 2:37 AM, Jonas Karlman wrote:
> This series make it possible to use more HDMI modes on RK3328,
> and presumably also on RK3228. It also prepares for a future YUV420 and
> 10-bit output series.
>
> Part of this has been reworked from vendor BSP 4.4 kernel commits.
>
> Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver.
>
> Patch 6 prepares for use of high TMDS bit rates used with HDMI 2.0 and
> 10-bit output modes.
>
> Patch 7-13 changes rk3228/rk3328 to use mode_valid functions suited for
> the inno hdmi phy instead of the dw-hdmi phy. These changes allows for
> more CEA modes to be usable, e.g. some 4K and fractal modes.
>
> Patch 14 adds support for more pixel clock rates in order to support
> common DMT modes in addition to CEA modes.
Is it possible to split the series targeted for different subsystems or
is it required for all the patches to be merged together?
Thanks
Kishon
>
> Note: I have only been able to build test RK322x related changes
> as I do not have any RK322x device to test on.
>
> All modes, including fractal modes, has been tested with modetest on
> a RK3328 Rock64 device using e.g.
>
> modetest -M rockchip -s 39:3840x2160-29.97
>
> Changes in v2:
> - collect acked-by tag
> - drop the limit resolution width to 3840 patch
>
> This series is also available at [1] and the early work on YUV420 and
> 10-bit output is available at [2].
>
> [1] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-inno-hdmi-phy
> [2] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-bus-format
>
> Regards,
> Jonas
>
> Algea Cao (1):
> phy/rockchip: inno-hdmi: Support more pre-pll configuration
>
> Huicong Xu (1):
> phy/rockchip: inno-hdmi: force set_rate on power_on
>
> Jonas Karlman (11):
> phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328
> phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate
> phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write
> drm/rockchip: dw-hdmi: allow high tmds bit rates
> drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328
> clk: rockchip: set parent rate for DCLK_VOP clock on rk3228
> arm64: dts: rockchip: increase vop clock rate on rk3328
> arm64: dts: rockchip: add vpll clock to hdmi node on rk3328
> ARM: dts: rockchip: add vpll clock to hdmi node on rk3228
> drm/rockchip: dw-hdmi: limit tmds to 340mhz on rk3228/rk3328
> drm/rockchip: dw-hdmi: remove unused plat_data on rk3228/rk3328
>
> Zheng Yang (1):
> phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate
>
> arch/arm/boot/dts/rk322x.dtsi | 4 +-
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +-
> drivers/clk/rockchip/clk-rk3228.c | 2 +-
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 47 ++++++--
> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------
> 5 files changed, 120 insertions(+), 49 deletions(-)
>
On 2020-01-10 12:01, Kishon Vijay Abraham I wrote:
>
>
> On 09/01/20 2:37 AM, Jonas Karlman wrote:
>> This series make it possible to use more HDMI modes on RK3328,
>> and presumably also on RK3228. It also prepares for a future YUV420 and
>> 10-bit output series.
>>
>> Part of this has been reworked from vendor BSP 4.4 kernel commits.
>>
>> Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver.
>>
>> Patch 6 prepares for use of high TMDS bit rates used with HDMI 2.0 and
>> 10-bit output modes.
>>
>> Patch 7-13 changes rk3228/rk3328 to use mode_valid functions suited for
>> the inno hdmi phy instead of the dw-hdmi phy. These changes allows for
>> more CEA modes to be usable, e.g. some 4K and fractal modes.
>>
>> Patch 14 adds support for more pixel clock rates in order to support
>> common DMT modes in addition to CEA modes.
>
> Is it possible to split the series targeted for different subsystems or
> is it required for all the patches to be merged together?
I think it should be possible to split the patches without any issue.
The phy changes mainly targets HDMI mode rates that is currently not in use,
filtered out by current mode_valid or YUV420/Deep Color modes not yet supported.
And the drm changes should not have a hard requirement on the phy changes
in this series, but I have not tested them separately.
I will split this series and re-run some tests before sending independent series.
Regards,
Jonas
>
> Thanks
> Kishon
>>
>> Note: I have only been able to build test RK322x related changes
>> as I do not have any RK322x device to test on.
>>
>> All modes, including fractal modes, has been tested with modetest on
>> a RK3328 Rock64 device using e.g.
>>
>> modetest -M rockchip -s 39:3840x2160-29.97
>>
>> Changes in v2:
>> - collect acked-by tag
>> - drop the limit resolution width to 3840 patch
>>
>> This series is also available at [1] and the early work on YUV420 and
>> 10-bit output is available at [2].
>>
>> [1] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-inno-hdmi-phy
>> [2] https://github.com/Kwiboo/linux-rockchip/commits/next-20200108-bus-format
>>
>> Regards,
>> Jonas
>>
>> Algea Cao (1):
>> phy/rockchip: inno-hdmi: Support more pre-pll configuration
>>
>> Huicong Xu (1):
>> phy/rockchip: inno-hdmi: force set_rate on power_on
>>
>> Jonas Karlman (11):
>> phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328
>> phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate
>> phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write
>> drm/rockchip: dw-hdmi: allow high tmds bit rates
>> drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328
>> clk: rockchip: set parent rate for DCLK_VOP clock on rk3228
>> arm64: dts: rockchip: increase vop clock rate on rk3328
>> arm64: dts: rockchip: add vpll clock to hdmi node on rk3328
>> ARM: dts: rockchip: add vpll clock to hdmi node on rk3228
>> drm/rockchip: dw-hdmi: limit tmds to 340mhz on rk3228/rk3328
>> drm/rockchip: dw-hdmi: remove unused plat_data on rk3228/rk3328
>>
>> Zheng Yang (1):
>> phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate
>>
>> arch/arm/boot/dts/rk322x.dtsi | 4 +-
>> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +-
>> drivers/clk/rockchip/clk-rk3228.c | 2 +-
>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 47 ++++++--
>> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------
>> 5 files changed, 120 insertions(+), 49 deletions(-)
>>
This is a long overdue revival of an old series that prepares support for
more HDMI modes, YUV420 and 10-bit output on RK3228/RK3328.
This v3 series contains the original v2 patches targeting the inno hdmi phy
driver, a separate series targeting drm driver should follow in a few days.
Part of this has been reworked from vendor BSP 4.4 kernel commits.
Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver.
Patch 6 adds support for more pixel clock rates in order to support
common DMT modes in addition to CEA modes.
Changes in v3:
- split series
- drop drm and device tree changes
Changes in v2:
- collect acked-by tag
- drop the limit resolution width to 3840 patch
This series is also available at [1].
[1] https://github.com/Kwiboo/linux-rockchip/commits/next-20200922-inno-hdmi-phy
Regards,
Jonas
Algea Cao (1):
phy/rockchip: inno-hdmi: Support more pre-pll configuration
Huicong Xu (1):
phy/rockchip: inno-hdmi: force set_rate on power_on
Jonas Karlman (3):
phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328
phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate
phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write
Zheng Yang (1):
phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------
1 file changed, 74 insertions(+), 36 deletions(-)
--
2.17.1
From: Algea Cao <[email protected]>
Adding the following freq cfg in 8-bit and 10-bit color depth:
{
40000000, 65000000, 71000000, 83500000, 85750000,
88750000, 108000000, 119000000, 162000000
}
New freq has been validated by quantumdata 980.
For some freq which can't be got by only using integer freq div,
frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
freq is different from the target freq, We must try to narrow
the gap between them. RK322X only support integer freq div.
The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
unlocked.
Signed-off-by: Algea Cao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ++++++++++++-------
1 file changed, 49 insertions(+), 25 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 3719309ad0d0..bb8bdf5e3301 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data {
const struct phy_config *phy_cfg_table;
};
+/*
+ * If only using integer freq div can't get frequency we want, frac
+ * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
+ * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different
+ * from the target frequency. Such as the tmds clock 110.9375 Mhz,
+ * the actual tmds clock we get is 110.93719 Mhz. It is important
+ * to note that RK322X platforms do not support frac div.
+ */
static const struct pre_pll_config pre_pll_cfg_table[] = {
- { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
- { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
- { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
- { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
- { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
- { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
- { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
- { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
- {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
- {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
- {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
- {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
- {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
- {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
- {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
- {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
- {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
- {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
- {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
- {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
- {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
+ { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
+ { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
+ { 40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
+ { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
+ { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
+ { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
+ { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
+ { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
+ { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000},
+ { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000},
+ {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
+ {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0},
+ {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0},
+ {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA},
+ {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
+ {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
+ {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0},
+ {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0},
+ {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
+ {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
+ {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
+ {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
+ {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
+ {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
{ /* sentinel */ }
};
--
2.17.1
This is a long overdue revival of an old series that adds support for
more HDMI modes on RK3228/RK3328.
This v3 series contains the original v2 patches targeting the inno hdmi phy
driver, a separate series targeting drm driver will follow, see [2] for
current work-in-progress of drm driver part.
Part of this has been reworked from vendor BSP 4.4 kernel commits.
Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver.
Patch 6 adds support for more pixel clock rates in order to support
common DMT modes in addition to CEA modes.
Changes in v3:
- split series
- drop drm and device tree changes
Changes in v2:
- collect acked-by tag
- drop the limit resolution width to 3840 patch
This series is also available at [1].
[1] https://github.com/Kwiboo/linux-rockchip/commits/next-20201009-inno-hdmi-phy
[2] https://github.com/Kwiboo/linux-rockchip/commits/next-20201009-drm-rockchip
Regards,
Jonas
Algea Cao (1):
phy/rockchip: inno-hdmi: Support more pre-pll configuration
Huicong Xu (1):
phy/rockchip: inno-hdmi: force set_rate on power_on
Jonas Karlman (3):
phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328
phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate
phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write
Zheng Yang (1):
phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------
1 file changed, 74 insertions(+), 36 deletions(-)
--
2.17.1
From: Algea Cao <[email protected]>
Adding the following freq cfg in 8-bit and 10-bit color depth:
{
40000000, 65000000, 71000000, 83500000, 85750000,
88750000, 108000000, 119000000, 162000000
}
New freq has been validated by quantumdata 980.
For some freq which can't be got by only using integer freq div,
frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
freq is different from the target freq, We must try to narrow
the gap between them. RK322X only support integer freq div.
The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
unlocked.
Signed-off-by: Algea Cao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ++++++++++++-------
1 file changed, 49 insertions(+), 25 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 3719309ad0d0..bb8bdf5e3301 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data {
const struct phy_config *phy_cfg_table;
};
+/*
+ * If only using integer freq div can't get frequency we want, frac
+ * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
+ * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different
+ * from the target frequency. Such as the tmds clock 110.9375 Mhz,
+ * the actual tmds clock we get is 110.93719 Mhz. It is important
+ * to note that RK322X platforms do not support frac div.
+ */
static const struct pre_pll_config pre_pll_cfg_table[] = {
- { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
- { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
- { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
- { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
- { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
- { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
- { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
- { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
- {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
- {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
- {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
- {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
- {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
- {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
- {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
- {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
- {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
- {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
- {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
- {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
- {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
+ { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
+ { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
+ { 40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
+ { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
+ { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
+ { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
+ { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
+ { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
+ { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000},
+ { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000},
+ {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
+ {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0},
+ {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0},
+ {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA},
+ {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
+ {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
+ {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
+ {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0},
+ {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0},
+ {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
+ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
+ {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
+ {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
+ {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
+ {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
+ {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
+ {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
+ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
{ /* sentinel */ }
};
--
2.17.1