This adds reset support for the Sparx5 SoC, using the ocelot reset
driver.
Changes in v2:
- Dropped the parts for resetting the switch core upon load time -
controlled by the 'microchip,reset-switch-core' DT property.
Lars Povlsen (3):
dt-bindings: reset: ocelot: Add Sparx5 support
power: reset: ocelot: Add support for Sparx5
arm64: dts: sparx5: Add reset support
.../bindings/power/reset/ocelot-reset.txt | 7 ++-
MAINTAINERS | 1 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++----
5 files changed, 60 insertions(+), 16 deletions(-)
--
2.25.1
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index a84ffd3069d4..016be6d27a6b 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -118,6 +118,16 @@ gic: interrupt-controller@600300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@611010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ };
+
uart0: serial@600100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.25.1
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <[email protected]>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
MAINTAINERS | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213eb3473..4d530d815484 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..cc70e3ab428b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11516,6 +11516,7 @@ M: Microchip Linux Driver Support <[email protected]>
L: [email protected]
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.25.1
On Tue, 06 Oct 2020 22:03:14 +0200, Lars Povlsen wrote:
> This adds the support for the Sparx5 SoC.
>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
> MAINTAINERS | 1 +
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
Hi,
On Tue, Oct 06, 2020 at 10:03:13PM +0200, Lars Povlsen wrote:
> This adds reset support for the Sparx5 SoC, using the ocelot reset
> driver.
>
> Changes in v2:
> - Dropped the parts for resetting the switch core upon load time -
> controlled by the 'microchip,reset-switch-core' DT property.
>
> Lars Povlsen (3):
> dt-bindings: reset: ocelot: Add Sparx5 support
> power: reset: ocelot: Add support for Sparx5
> arm64: dts: sparx5: Add reset support
>
> .../bindings/power/reset/ocelot-reset.txt | 7 ++-
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 10 ++++
> drivers/power/reset/Kconfig | 3 +-
> drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++----
> 5 files changed, 60 insertions(+), 16 deletions(-)
Thanks, I queued the first two patches.
-- Sebastian