On Wed, Oct 14, 2020 at 8:50 AM Dhananjay Phadke
<[email protected]> wrote:
>
> On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> > --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> > +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
> >
> > - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > - /* Start of SMBUS for Master Read */
> > + I2C_SLAVE_WRITE_REQUESTED, &rx_data);
> > + iproc_i2c->rx_start_rcvd = true;
> > + iproc_i2c->slave_read_complete = false;
> > + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> > + iproc_i2c->rx_start_rcvd) {
> > + /* Middle of SMBUS Master write */
> > i2c_slave_event(iproc_i2c->slave,
> > - I2C_SLAVE_READ_REQUESTED, &value);
> > - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> > + I2C_SLAVE_WRITE_RECEIVED, &rx_data);
> > + } else if (rx_status == I2C_SLAVE_RX_END &&
> > + iproc_i2c->rx_start_rcvd) {
> > + /* End of SMBUS Master write */
> > + if (iproc_i2c->slave_rx_only)
> > + i2c_slave_event(iproc_i2c->slave,
> > + I2C_SLAVE_WRITE_RECEIVED,
> > + &rx_data);
> > +
> > + i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
> > + &rx_data);
> > + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> > + iproc_i2c->rx_start_rcvd = false;
> > + iproc_i2c->slave_read_complete = true;
> > + break;
> > + }
> >
> > - val = BIT(S_CMD_START_BUSY_SHIFT);
> > - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> > + rx_bytes++;
>
> rx_bytes should be incremented only along with I2C_SLAVE_WRITE_RECEIVED event?
It should be incremented in both I2C_SLAVE_WRITE_REQUESTED and
I2C_SLAVE_WRITE_RECEIVED cases because in both cases it is reading
valid bytes from rx fifo.
>
> >
> > +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
> > + u32 status)
> > +{
> > + u32 val;
> > + u8 value;
> > +
> > + /*
> > + * Slave events in case of master-write, master-write-read and,
> > + * master-read
> > + *
> > + * Master-write : only IS_S_RX_EVENT_SHIFT event
> > + * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> > + * events
> > + * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> > + * events or only IS_S_RD_EVENT_SHIFT
> > + */
> > + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> > + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > + /* disable slave interrupts */
> > + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> > + val &= ~iproc_i2c->slave_int_mask;
> > + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> > +
> > + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> > + /* Master-write-read request */
> > + iproc_i2c->slave_rx_only = false;
> > + else
> > + /* Master-write request only */
> > + iproc_i2c->slave_rx_only = true;
> > +
> > + /* schedule tasklet to read data later */
> > + tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
> > +
> > + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> > + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> > + BIT(IS_S_RX_EVENT_SHIFT));
> >
>
> Both tasklet and isr are writing to status (IS_OFFSET) reg.
>
> The tasklet seems to be batching up rx fifo reads because of time-sensitive
> Master-write-read transaction? Linux I2C framework is byte interface anyway.
> Can the need to batch reads be avoided by setting slave rx threshold for
> interrupt (S_FIFO_RX_THLD) to 1-byte?
To process more data with a single interrupt we are batching up rx fifo reads.
This will reduce the number of interrupts.
Also to avoid tasklet running more time (20us) we have a threshold of
10 bytes for batching read.
This is a better/optimised approach than reading single byte data per interrupt.
>
> Also, wouldn't tasklets be susceptible to other interrupts? If fifo reads
> have to be batched up, can it be changed to threaded irq?
tasklets have higher priority than threaded irq, since i2c is time
sensitive so using a tasklet is preferred over threaded irq.
Best regards,
Rayagonda
>
>
On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
>
> - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> - /* Start of SMBUS for Master Read */
> + I2C_SLAVE_WRITE_REQUESTED, &rx_data);
> + iproc_i2c->rx_start_rcvd = true;
> + iproc_i2c->slave_read_complete = false;
> + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> + iproc_i2c->rx_start_rcvd) {
> + /* Middle of SMBUS Master write */
> i2c_slave_event(iproc_i2c->slave,
> - I2C_SLAVE_READ_REQUESTED, &value);
> - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> + I2C_SLAVE_WRITE_RECEIVED, &rx_data);
> + } else if (rx_status == I2C_SLAVE_RX_END &&
> + iproc_i2c->rx_start_rcvd) {
> + /* End of SMBUS Master write */
> + if (iproc_i2c->slave_rx_only)
> + i2c_slave_event(iproc_i2c->slave,
> + I2C_SLAVE_WRITE_RECEIVED,
> + &rx_data);
> +
> + i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
> + &rx_data);
> + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> + iproc_i2c->rx_start_rcvd = false;
> + iproc_i2c->slave_read_complete = true;
> + break;
> + }
>
> - val = BIT(S_CMD_START_BUSY_SHIFT);
> - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> + rx_bytes++;
rx_bytes should be incremented only along with I2C_SLAVE_WRITE_RECEIVED event?
>
> +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
> + u32 status)
> +{
> + u32 val;
> + u8 value;
> +
> + /*
> + * Slave events in case of master-write, master-write-read and,
> + * master-read
> + *
> + * Master-write : only IS_S_RX_EVENT_SHIFT event
> + * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + * events
> + * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + * events or only IS_S_RD_EVENT_SHIFT
> + */
> + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> + /* disable slave interrupts */
> + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> + val &= ~iproc_i2c->slave_int_mask;
> + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> +
> + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> + /* Master-write-read request */
> + iproc_i2c->slave_rx_only = false;
> + else
> + /* Master-write request only */
> + iproc_i2c->slave_rx_only = true;
> +
> + /* schedule tasklet to read data later */
> + tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
> +
> + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> + BIT(IS_S_RX_EVENT_SHIFT));
>
Both tasklet and isr are writing to status (IS_OFFSET) reg.
The tasklet seems to be batching up rx fifo reads because of time-sensitive
Master-write-read transaction? Linux I2C framework is byte interface anyway.
Can the need to batch reads be avoided by setting slave rx threshold for
interrupt (S_FIFO_RX_THLD) to 1-byte?
Also, wouldn't tasklets be susceptible to other interrupts? If fifo reads
have to be batched up, can it be changed to threaded irq?
On 10/13/2020 10:12 PM, Rayagonda Kokatanur wrote:
>
>
> On Wed, Oct 14, 2020 at 8:50 AM Dhananjay Phadke
> <[email protected] <mailto:[email protected]>> wrote:
>
> On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> > --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> > +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
> >
> > - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > - /* Start of SMBUS for Master Read */
> > + I2C_SLAVE_WRITE_REQUESTED,
> &rx_data);
> > + iproc_i2c->rx_start_rcvd = true;
> > + iproc_i2c->slave_read_complete = false;
> > + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> > + iproc_i2c->rx_start_rcvd) {
> > + /* Middle of SMBUS Master write */
> > i2c_slave_event(iproc_i2c->slave,
> > - I2C_SLAVE_READ_REQUESTED,
> &value);
> > - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> > + I2C_SLAVE_WRITE_RECEIVED,
> &rx_data);
> > + } else if (rx_status == I2C_SLAVE_RX_END &&
> > + iproc_i2c->rx_start_rcvd) {
> > + /* End of SMBUS Master write */
> > + if (iproc_i2c->slave_rx_only)
> > + i2c_slave_event(iproc_i2c->slave,
> > +
> I2C_SLAVE_WRITE_RECEIVED,
> > + &rx_data);
> > +
> > + i2c_slave_event(iproc_i2c->slave,
> I2C_SLAVE_STOP,
> > + &rx_data);
> > + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> > + iproc_i2c->rx_start_rcvd = false;
> > + iproc_i2c->slave_read_complete = true;
> > + break;
> > + }
> >
> > - val = BIT(S_CMD_START_BUSY_SHIFT);
> > - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> > + rx_bytes++;
>
> rx_bytes should be incremented only along with
> I2C_SLAVE_WRITE_RECEIVED event?
>
>
> It should be incremented in both I2C_SLAVE_WRITE_REQUESTED and
> I2C_SLAVE_WRITE_RECEIVED cases because in both case it is reading valid
> bytes from rx fifo.
>
>
> >
> > +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev
> *iproc_i2c,
> > + u32 status)
> > +{
> > + u32 val;
> > + u8 value;
> > +
> > + /*
> > + * Slave events in case of master-write, master-write-read and,
> > + * master-read
> > + *
> > + * Master-write : only IS_S_RX_EVENT_SHIFT event
> > + * Master-write-read: both IS_S_RX_EVENT_SHIFT and
> IS_S_RD_EVENT_SHIFT
> > + * events
> > + * Master-read : both IS_S_RX_EVENT_SHIFT and
> IS_S_RD_EVENT_SHIFT
> > + * events or only IS_S_RD_EVENT_SHIFT
> > + */
> > + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> > + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > + /* disable slave interrupts */
> > + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> > + val &= ~iproc_i2c->slave_int_mask;
> > + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> > +
> > + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> > + /* Master-write-read request */
> > + iproc_i2c->slave_rx_only = false;
> > + else
> > + /* Master-write request only */
> > + iproc_i2c->slave_rx_only = true;
> > +
> > + /* schedule tasklet to read data later */
> > + tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
> > +
> > + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> > + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> > + BIT(IS_S_RX_EVENT_SHIFT));
> >
>
> Both tasklet and isr are writing to status (IS_OFFSET) reg.
>
>
> Yes this is required.
>
> For ex, If IS_S_RD_EVENT_SHIFT interrupt, this should be cleared once
> the driver completes reading all data from rx fifo.
> After this the driver can start sending data to master.
>
If both tasklet and isr are accessing the IS_OFFSET register, don't you
need lock protection against race condition? That is, ISR can interrupt
tasklet.
>
>
> The tasklet seems to be batching up rx fifo reads because of
> time-sensitive
> Master-write-read transaction? Linux I2C framework is byte interface
> anyway.
> Can the need to batch reads be avoided by setting slave rx threshold for
> interrupt (S_FIFO_RX_THLD) to 1-byte?
>
>
> To process more data with a single interrupt we are batching up rx fifo
> reads.
> This will reduce the number of interrupts.
>
> Also to avoid tasklet running more time (20us) we have a threshold of 10
> bytes for batching read.
> This is a better/optimised approach than reading single byte data per
> interrupt.
>
>
> Also, wouldn't tasklets be susceptible to other interrupts? If fifo
> reads
> have to be batched up, can it be changed to threaded irq?
>
>
> tasklets have higher priority than threaded irq, since i2c is time
> sensitive so using a tasklet is preferred over threaded irq.
>
On Fri, Oct 23, 2020 at 10:56 PM Ray Jui <[email protected]> wrote:
>
>
>
> On 10/13/2020 10:12 PM, Rayagonda Kokatanur wrote:
> >
> >
> > On Wed, Oct 14, 2020 at 8:50 AM Dhananjay Phadke
> > <[email protected] <mailto:[email protected]>> wrote:
> >
> > On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> > > --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> > > +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
> > >
> > > - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > > - /* Start of SMBUS for Master Read */
> > > + I2C_SLAVE_WRITE_REQUESTED,
> > &rx_data);
> > > + iproc_i2c->rx_start_rcvd = true;
> > > + iproc_i2c->slave_read_complete = false;
> > > + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> > > + iproc_i2c->rx_start_rcvd) {
> > > + /* Middle of SMBUS Master write */
> > > i2c_slave_event(iproc_i2c->slave,
> > > - I2C_SLAVE_READ_REQUESTED,
> > &value);
> > > - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> > > + I2C_SLAVE_WRITE_RECEIVED,
> > &rx_data);
> > > + } else if (rx_status == I2C_SLAVE_RX_END &&
> > > + iproc_i2c->rx_start_rcvd) {
> > > + /* End of SMBUS Master write */
> > > + if (iproc_i2c->slave_rx_only)
> > > + i2c_slave_event(iproc_i2c->slave,
> > > +
> > I2C_SLAVE_WRITE_RECEIVED,
> > > + &rx_data);
> > > +
> > > + i2c_slave_event(iproc_i2c->slave,
> > I2C_SLAVE_STOP,
> > > + &rx_data);
> > > + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> > > + iproc_i2c->rx_start_rcvd = false;
> > > + iproc_i2c->slave_read_complete = true;
> > > + break;
> > > + }
> > >
> > > - val = BIT(S_CMD_START_BUSY_SHIFT);
> > > - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> > > + rx_bytes++;
> >
> > rx_bytes should be incremented only along with
> > I2C_SLAVE_WRITE_RECEIVED event?
> >
> >
> > It should be incremented in both I2C_SLAVE_WRITE_REQUESTED and
> > I2C_SLAVE_WRITE_RECEIVED cases because in both case it is reading valid
> > bytes from rx fifo.
> >
> >
> > >
> > > +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev
> > *iproc_i2c,
> > > + u32 status)
> > > +{
> > > + u32 val;
> > > + u8 value;
> > > +
> > > + /*
> > > + * Slave events in case of master-write, master-write-read and,
> > > + * master-read
> > > + *
> > > + * Master-write : only IS_S_RX_EVENT_SHIFT event
> > > + * Master-write-read: both IS_S_RX_EVENT_SHIFT and
> > IS_S_RD_EVENT_SHIFT
> > > + * events
> > > + * Master-read : both IS_S_RX_EVENT_SHIFT and
> > IS_S_RD_EVENT_SHIFT
> > > + * events or only IS_S_RD_EVENT_SHIFT
> > > + */
> > > + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> > > + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> > > + /* disable slave interrupts */
> > > + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> > > + val &= ~iproc_i2c->slave_int_mask;
> > > + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> > > +
> > > + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> > > + /* Master-write-read request */
> > > + iproc_i2c->slave_rx_only = false;
> > > + else
> > > + /* Master-write request only */
> > > + iproc_i2c->slave_rx_only = true;
> > > +
> > > + /* schedule tasklet to read data later */
> > > + tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
> > > +
> > > + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> > > + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> > > + BIT(IS_S_RX_EVENT_SHIFT));
> > >
> >
> > Both tasklet and isr are writing to status (IS_OFFSET) reg.
> >
> >
> > Yes this is required.
> >
> > For ex, If IS_S_RD_EVENT_SHIFT interrupt, this should be cleared once
> > the driver completes reading all data from rx fifo.
> > After this the driver can start sending data to master.
> >
>
> If both tasklet and isr are accessing the IS_OFFSET register, don't you
> need lock protection against race condition? That is, ISR can interrupt
> tasklet.
All interrupts are disbaled when the tasklet is running.
Interrupts are re-enabled at the end of the tasklet.
So no race condition between tasklet and isr.
Best regards,
Rayagonda
>
> >
> >
> > The tasklet seems to be batching up rx fifo reads because of
> > time-sensitive
> > Master-write-read transaction? Linux I2C framework is byte interface
> > anyway.
> > Can the need to batch reads be avoided by setting slave rx threshold for
> > interrupt (S_FIFO_RX_THLD) to 1-byte?
> >
> >
> > To process more data with a single interrupt we are batching up rx fifo
> > reads.
> > This will reduce the number of interrupts.
> >
> > Also to avoid tasklet running more time (20us) we have a threshold of 10
> > bytes for batching read.
> > This is a better/optimised approach than reading single byte data per
> > interrupt.
> >
> >
> > Also, wouldn't tasklets be susceptible to other interrupts? If fifo
> > reads
> > have to be batched up, can it be changed to threaded irq?
> >
> >
> > tasklets have higher priority than threaded irq, since i2c is time
> > sensitive so using a tasklet is preferred over threaded irq.
> >