LinuxLists.cc - [PATCH 3/5] memory: tegra: Sort tegra210

2020-10-08 00:54:11

Subject: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

This is a cleanup change to prepare for new swgroups.

Signed-off-by: Nicolin Chen <[email protected]>
---
drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index e8a7d266802c..b400802c9f14 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
};

static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
- { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
- { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
- { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
+ { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
+ { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
+ { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
+ { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
- { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
+ { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
+ { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
- { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
- { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
- { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
+ { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
- { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
- { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
+ { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
+ { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
- { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
+ { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
--
2.17.1

2020-10-08 16:37:44

by Krzysztof Kozlowski

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Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.

What type of cleanup? Any functional change?

>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index e8a7d266802c..b400802c9f14 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> };
>
> static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
> { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
> - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
> + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
> { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
> - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
> { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
> - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },

I must say I cannot find the order. By name - not. By swgroup name -
not. By register - not.

What is the order then?

Best regards,
Krzysztof

> - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
> { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
> { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
> { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
> - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
> { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
> - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
> + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
> { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
> { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
> --
> 2.17.1
>

2020-10-08 21:39:21

by Nicolin Chen

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Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

Hi Krzysztof,

On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > This is a cleanup change to prepare for new swgroups.
>
> What type of cleanup? Any functional change?

It's to sort the swgroup list by reg address as I mentioned in
the subject. Perhaps I should have put in commit message also.

> >
> > Signed-off-by: Nicolin Chen <[email protected]>
> > ---
> > drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> > index e8a7d266802c..b400802c9f14 100644
> > --- a/drivers/memory/tegra/tegra210.c
> > +++ b/drivers/memory/tegra/tegra210.c
> > @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> > };
> >
> > static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> > - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> > - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> > { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
> > { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
> > - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> > + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> > { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
> > + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> > { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
> > { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
> > - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> > + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> > { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
> > { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
> > - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> > - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> > { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
>
> I must say I cannot find the order. By name - not. By swgroup name -
> not. By register - not.
>
> What is the order then?

It's by "reg" as I mentioned in the commit subject. Probably
it's not that obvious by looking at the change itself :-/

Its following change of adding new swgroups would be easier
to insert by following the same order of "reg" addresses.

Thanks

2020-10-09 13:07:23

by Thierry Reding

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Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)

Acked-by: Thierry Reding <[email protected]>

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2020-10-12 16:48:17

by Krzysztof Kozlowski

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Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote:
> Hi Krzysztof,
>
> On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > > This is a cleanup change to prepare for new swgroups.
> >
> > What type of cleanup? Any functional change?
>
> It's to sort the swgroup list by reg address as I mentioned in
> the subject. Perhaps I should have put in commit message also.

Indeed it is sorted by regs, I missed some numbers... looks good. I can
adjust the commit msg so no need for resend.

Best regards,
Krzysztof

2020-10-13 08:56:11

by Nicolin Chen

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Subject: Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address

On Mon, Oct 12, 2020 at 06:43:40PM +0200, Krzysztof Kozlowski wrote:
> On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote:
> > Hi Krzysztof,
> >
> > On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > > > This is a cleanup change to prepare for new swgroups.
> > >
> > > What type of cleanup? Any functional change?
> >
> > It's to sort the swgroup list by reg address as I mentioned in
> > the subject. Perhaps I should have put in commit message also.
>
> Indeed it is sorted by regs, I missed some numbers... looks good. I can
> adjust the commit msg so no need for resend.

Thank you!

2020-10-27 06:56:22

by Krzysztof Kozlowski

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