Change in v7:
1)add "unevaluatedProperties" in mtk-sd.yaml
2)add Reviewed-by tag
Change in v6:
1)use devm_clk_get function for required clocks
Change in v5:
1)remove Reviewed-by tag
2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional
for bulk clks
Change in v4:
1)drop "vmmc" and "vqmmc" desciption in mtk-sd.yaml
2)add vmmq/vqmmc supplies and the pinctrls to required properties
3)change dbg level and exit this function
4)use devm_clk_get_optional instead of devm_clk_get function
5)remove else branch for sys_clk_cg
Change in v3:
1)change maintainers name in mtk-sd.yaml
2)change "compatible" properties to enum type and sort it
3)drop these properties: "reg" and "interrupts"
4)add "maxItems" constraints on these properties: "vmmc-supply", "vqmmc-supply",
"assigned-clocks", "assigned-clock-parents"
5)add "minimum" and "maximum" constraints on these properties: "mediatek,hs400-cmd-int-delay",
"mediatek,latch-ck", "hs400-ds-delay", "mediatek,hs200-cmd-int-delay"
Change in v2:
Convert mtk-sd to json-schema
Wenbin Mei (4):
dt-bindings: mmc: Convert mtk-sd to json-schema
mmc: dt-bindings: add support for MT8192 SoC
arm64: dts: mt8192: add mmc device node
mmc: mediatek: Add subsys clock control for MT8192 msdc
---
This patch depends on
[v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
[v3,1/9] dt-bindings: ARM: Mediatek: Document bindings for MT8192 BSP
[v3,6/9] clk: mediatek: Add dt-bindings for MT8192 clocks
[v3,9/9] clk: mediatek: Add MT8192 clock support
[v3,1/3] dt-bindings: pinctrl: mt8192: add pinctrl file
[v3,2/3] dt-bindings: pinctrl: mt8192: add binding document
[v3,3/3] pinctrl: add pinctrl driver on mt8192
[v2,1/4] soc: mediatek: pwrap: use BIT() macro
[v2,2/4] soc: mediatek: pwrap: add arbiter capability
[v2,3/4] dt-bindings: mediatek: add compatible for MT6873/8192 pwrap
[v2,4/4] soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs
[2/8] dt-bindings: mfd: Add compatible for the MediaTek MT6359 PMIC
[3/8] dt-bindings: regulator: Add document for MT6359 regulator
[4/8] mfd: Add support for the MediaTek MT6359 PMIC
[5/8] regulator: mt6359: Add support for MT6359 regulator
[7/8] regulator: mt6359: Add support for MT6359P regulator
[8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes
Please also accept this patch together with [1][2][3][4][5]
to avoid build and dt binding check error.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=332621
[2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=342593
[3] https://patchwork.kernel.org/project/linux-mediatek/list/?series=330017
[4] https://patchwork.kernel.org/project/linux-mediatek/list/?series=322937
[5] https://patchwork.kernel.org/project/linux-mediatek/list/?series=323171
---
.../devicetree/bindings/mmc/mtk-sd.txt | 75 --------
.../devicetree/bindings/mmc/mtk-sd.yaml | 176 ++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++
drivers/mmc/host/mtk-sd.c | 74 ++++++--
5 files changed, 355 insertions(+), 93 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
--
2.18.0
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/mmc/mtk-sd.txt | 75 --------
.../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++++++++++++++++++
2 files changed, 165 insertions(+), 75 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
deleted file mode 100644
index 26a8f320a156..000000000000
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-* MTK MMC controller
-
-The MTK MSDC can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the msdc driver.
-
-Required properties:
-- compatible: value should be either of the following.
- "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
- "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
- "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
- "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
- "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
- "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
- "mediatek,mt7622-mmc": for MT7622 SoC
- "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- "mediatek,mt7620-mmc", for MT7621 SoC (and others)
-
-- reg: physical base address of the controller and length
-- interrupts: Should contain MSDC interrupt number
-- clocks: Should contain phandle for the clock feeding the MMC controller
-- clock-names: Should contain the following:
- "source" - source clock (required)
- "hclk" - HCLK which used for host (required)
- "source_cg" - independent source clock gate (required for MT2712)
- "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin ctrl
-- pinctrl-1: should contain uhs mode pin ctrl
-- vmmc-supply: power to the Core
-- vqmmc-supply: power to the IO
-
-Optional properties:
-- assigned-clocks: PLL of the source clock
-- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
-- hs400-ds-delay: HS400 DS delay setting
-- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
- If present,HS400 command responses are sampled on rising edges.
- If not present,HS400 command responses are sampled on falling edges.
-- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
- error caused by stop clock(fifo full)
- Valid range = [0:0x7]. if not present, default value is 0.
- applied to compatible "mediatek,mt2701-mmc".
-- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
-- reset-names: Should be "hrst".
-
-Examples:
-mmc0: mmc@11230000 {
- compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
- reg = <0 0x11230000 0 0x108>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
- vmmc-supply = <&mt6397_vemc_3v3_reg>;
- vqmmc-supply = <&mt6397_vio18_reg>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_default>;
- pinctrl-1 = <&mmc0_pins_uhs>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
- hs400-ds-delay = <0x14015>;
- mediatek,hs200-cmd-int-delay = <26>;
- mediatek,hs400-cmd-int-delay = <14>;
- mediatek,hs400-cmd-resp-sel-rising;
-};
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
new file mode 100644
index 000000000000..79905df75f1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTK MSDC Storage Host Controller Binding
+
+maintainers:
+ - Chaotian Jing <[email protected]>
+ - Wenbin Mei <[email protected]>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-mmc
+ - mediatek,mt2712-mmc
+ - mediatek,mt6779-mmc
+ - mediatek,mt7620-mmc
+ - mediatek,mt7622-mmc
+ - mediatek,mt8135-mmc
+ - mediatek,mt8173-mmc
+ - mediatek,mt8183-mmc
+ - mediatek,mt8516-mmc
+ - items:
+ - const: mediatek,mt7623-mmc
+ - const: mediatek,mt2701-mmc
+
+ clocks:
+ description:
+ Should contain phandle for the clock feeding the MMC controller.
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: source clock (required).
+ - description: HCLK which used for host (required).
+ - description: independent source clock gate (required for MT2712).
+ - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: source
+ - const: hclk
+ - const: source_cg
+ - const: bus_clk
+
+ pinctrl-names:
+ items:
+ - const: default
+ - const: state_uhs
+
+ pinctrl-0:
+ description:
+ should contain default/high speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-1:
+ description:
+ should contain uhs mode pin ctrl.
+ maxItems: 1
+
+ assigned-clocks:
+ description:
+ PLL of the source clock.
+ maxItems: 1
+
+ assigned-clock-parents:
+ description:
+ parent of source clock, used for HS400 mode to get 400Mhz source clock.
+ maxItems: 1
+
+ hs400-ds-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 DS delay setting.
+ minimum: 0
+ maximum: 0xffffffff
+
+ mediatek,hs200-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS200 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-resp-sel-rising:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ HS400 command response sample selection.
+ If present, HS400 command responses are sampled on rising edges.
+ If not present, HS400 command responses are sampled on falling edges.
+
+ mediatek,latch-ck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
+ data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
+ if not present, default value is 0.
+ applied to compatible "mediatek,mt2701-mmc".
+ minimum: 0
+ maximum: 7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: hrst
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - pinctrl-names
+ - pinctrl-0
+ - pinctrl-1
+ - vmmc-supply
+ - vqmmc-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8173-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ vmmc-supply = <&mt6397_vemc_3v3_reg>;
+ vqmmc-supply = <&mt6397_vio18_reg>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ hs400-ds-delay = <0x14015>;
+ mediatek,hs200-cmd-int-delay = <26>;
+ mediatek,hs400-cmd-int-delay = <14>;
+ mediatek,hs400-cmd-resp-sel-rising;
+ };
+
+...
--
2.18.0
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei <[email protected]>
Reviewed-by: Nicolas Boichat <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 74 +++++++++++++++++++++++++++++----------
1 file changed, 56 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index a704745e5882..c7df7510f120 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -35,6 +35,7 @@
#include "cqhci.h"
#define MAX_BD_NUM 1024
+#define MSDC_NR_CLOCKS 3
/*--------------------------------------------------------------------------*/
/* Common Definition */
@@ -425,6 +426,8 @@ struct msdc_host {
struct clk *h_clk; /* msdc h_clk */
struct clk *bus_clk; /* bus clock which used to access register */
struct clk *src_clk_cg; /* msdc source clock control gate */
+ struct clk *sys_clk_cg; /* msdc subsys clock control gate */
+ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
unsigned char timing;
@@ -784,6 +787,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
static void msdc_gate_clock(struct msdc_host *host)
{
+ clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
clk_disable_unprepare(host->src_clk_cg);
clk_disable_unprepare(host->src_clk);
clk_disable_unprepare(host->bus_clk);
@@ -792,10 +796,18 @@ static void msdc_gate_clock(struct msdc_host *host)
static void msdc_ungate_clock(struct msdc_host *host)
{
+ int ret;
+
clk_prepare_enable(host->h_clk);
clk_prepare_enable(host->bus_clk);
clk_prepare_enable(host->src_clk);
clk_prepare_enable(host->src_clk_cg);
+ ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
+ if (ret) {
+ dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
+ return;
+ }
+
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
}
@@ -2366,6 +2378,48 @@ static void msdc_of_property_parse(struct platform_device *pdev,
host->cqhci = false;
}
+static int msdc_of_clock_parse(struct platform_device *pdev,
+ struct msdc_host *host)
+{
+ int ret;
+
+ host->src_clk = devm_clk_get(&pdev->dev, "source");
+ if (IS_ERR(host->src_clk))
+ return PTR_ERR(host->src_clk);
+
+ host->h_clk = devm_clk_get(&pdev->dev, "hclk");
+ if (IS_ERR(host->h_clk))
+ return PTR_ERR(host->h_clk);
+
+ host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
+ if (IS_ERR(host->bus_clk))
+ host->bus_clk = NULL;
+
+ /*source clock control gate is optional clock*/
+ host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
+ if (IS_ERR(host->src_clk_cg))
+ host->src_clk_cg = NULL;
+
+ host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg");
+ if (IS_ERR(host->sys_clk_cg))
+ host->sys_clk_cg = NULL;
+
+ /* If present, always enable for this clock gate */
+ clk_prepare_enable(host->sys_clk_cg);
+
+ host->bulk_clks[0].id = "pclk_cg";
+ host->bulk_clks[1].id = "axi_cg";
+ host->bulk_clks[2].id = "ahb_cg";
+ ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
+ host->bulk_clks);
+ if (ret) {
+ dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int msdc_drv_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
@@ -2405,25 +2459,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
if (ret)
goto host_free;
- host->src_clk = devm_clk_get(&pdev->dev, "source");
- if (IS_ERR(host->src_clk)) {
- ret = PTR_ERR(host->src_clk);
- goto host_free;
- }
-
- host->h_clk = devm_clk_get(&pdev->dev, "hclk");
- if (IS_ERR(host->h_clk)) {
- ret = PTR_ERR(host->h_clk);
+ ret = msdc_of_clock_parse(pdev, host);
+ if (ret)
goto host_free;
- }
-
- host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
- if (IS_ERR(host->bus_clk))
- host->bus_clk = NULL;
- /*source clock control gate is optional clock*/
- host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
- if (IS_ERR(host->src_clk_cg))
- host->src_clk_cg = NULL;
host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
"hrst");
--
2.18.0
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&pio {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
--
2.18.0
MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei <[email protected]>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 79905df75f1d..030e3fdce492 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -29,26 +29,37 @@ properties:
- items:
- const: mediatek,mt7623-mmc
- const: mediatek,mt2701-mmc
+ - items:
+ - const: mediatek,mt8192-mmc
+ - const: mediatek,mt8183-mmc
clocks:
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: msdc subsys clock gate (required for MT8192).
+ - description: peripheral bus clock gate (required for MT8192).
+ - description: AXI bus clock gate (required for MT8192).
+ - description: AHB bus clock gate (required for MT8192).
clock-names:
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- const: source
- const: hclk
- const: source_cg
- const: bus_clk
+ - const: sys_cg
+ - const: pclk_cg
+ - const: axi_cg
+ - const: ahb_cg
pinctrl-names:
items:
--
2.18.0
On Wed, 14 Oct 2020 11:08:44 +0800, Wenbin Mei wrote:
> MT8192 mmc host ip is compatible with MT8183.
> Add support for this.
>
> Signed-off-by: Wenbin Mei <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
On Wed, 14 Oct 2020 at 05:08, Wenbin Mei <[email protected]> wrote:
>
> Change in v7:
> 1)add "unevaluatedProperties" in mtk-sd.yaml
> 2)add Reviewed-by tag
>
> Change in v6:
> 1)use devm_clk_get function for required clocks
>
> Change in v5:
> 1)remove Reviewed-by tag
> 2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional
> for bulk clks
>
> Change in v4:
> 1)drop "vmmc" and "vqmmc" desciption in mtk-sd.yaml
> 2)add vmmq/vqmmc supplies and the pinctrls to required properties
> 3)change dbg level and exit this function
> 4)use devm_clk_get_optional instead of devm_clk_get function
> 5)remove else branch for sys_clk_cg
>
> Change in v3:
> 1)change maintainers name in mtk-sd.yaml
> 2)change "compatible" properties to enum type and sort it
> 3)drop these properties: "reg" and "interrupts"
> 4)add "maxItems" constraints on these properties: "vmmc-supply", "vqmmc-supply",
> "assigned-clocks", "assigned-clock-parents"
> 5)add "minimum" and "maximum" constraints on these properties: "mediatek,hs400-cmd-int-delay",
> "mediatek,latch-ck", "hs400-ds-delay", "mediatek,hs200-cmd-int-delay"
>
> Change in v2:
> Convert mtk-sd to json-schema
>
> Wenbin Mei (4):
> dt-bindings: mmc: Convert mtk-sd to json-schema
> mmc: dt-bindings: add support for MT8192 SoC
> arm64: dts: mt8192: add mmc device node
> mmc: mediatek: Add subsys clock control for MT8192 msdc
> ---
> This patch depends on
> [v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
> [v3,1/9] dt-bindings: ARM: Mediatek: Document bindings for MT8192 BSP
> [v3,6/9] clk: mediatek: Add dt-bindings for MT8192 clocks
> [v3,9/9] clk: mediatek: Add MT8192 clock support
> [v3,1/3] dt-bindings: pinctrl: mt8192: add pinctrl file
> [v3,2/3] dt-bindings: pinctrl: mt8192: add binding document
> [v3,3/3] pinctrl: add pinctrl driver on mt8192
> [v2,1/4] soc: mediatek: pwrap: use BIT() macro
> [v2,2/4] soc: mediatek: pwrap: add arbiter capability
> [v2,3/4] dt-bindings: mediatek: add compatible for MT6873/8192 pwrap
> [v2,4/4] soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs
> [2/8] dt-bindings: mfd: Add compatible for the MediaTek MT6359 PMIC
> [3/8] dt-bindings: regulator: Add document for MT6359 regulator
> [4/8] mfd: Add support for the MediaTek MT6359 PMIC
> [5/8] regulator: mt6359: Add support for MT6359 regulator
> [7/8] regulator: mt6359: Add support for MT6359P regulator
> [8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes
>
> Please also accept this patch together with [1][2][3][4][5]
> to avoid build and dt binding check error.
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=332621
> [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=342593
> [3] https://patchwork.kernel.org/project/linux-mediatek/list/?series=330017
> [4] https://patchwork.kernel.org/project/linux-mediatek/list/?series=322937
> [5] https://patchwork.kernel.org/project/linux-mediatek/list/?series=323171
> ---
> .../devicetree/bindings/mmc/mtk-sd.txt | 75 --------
> .../devicetree/bindings/mmc/mtk-sd.yaml | 176 ++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++
> drivers/mmc/host/mtk-sd.c | 74 ++++++--
> 5 files changed, 355 insertions(+), 93 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>
> --
> 2.18.0
>
Applied for next, except patch 3 as needs to go via arm-soc, thanks!
Kind regards
Uffe