Hello
The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The
PHY is capable of 10Mbps communication over long distances and exceeds the
IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports
various voltage level signalling and can be forced to support a specific
voltage or allowed to perfrom auto negotiation on the voltage level. The
default for the PHY is auto negotiation but if the PHY is forced to a specific
voltage then the LP must also support the same voltage.
Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's
capability.
Dan
Dan Murphy (4):
ethtool: Add 10base-T1L link mode entries
dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
.../devicetree/bindings/net/ethernet-phy.yaml | 5 +
.../devicetree/bindings/net/ti,dp83td510.yaml | 62 ++
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/dp83td510.c | 681 ++++++++++++++++++
drivers/net/phy/phy-core.c | 4 +-
include/uapi/linux/ethtool.h | 2 +
net/ethtool/common.c | 2 +
net/ethtool/linkmodes.c | 2 +
9 files changed, 764 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
create mode 100644 drivers/net/phy/dp83td510.c
--
2.28.0.585.ge1cfff676549
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TP ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x00000000 (0)
Link detected: yes
Signed-off-by: Dan Murphy <[email protected]>
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(400000, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.28.0.585.ge1cfff676549
Per the 802.3cg spec the 10base T1L can operate at 2 different
differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to
drive that output is dependent on the PHY's on board power supply.
This common feature is applicable to all 10base T1L PHYs so this binding
property belongs in a top level ethernet document.
Signed-off-by: Dan Murphy <[email protected]>
---
Documentation/devicetree/bindings/net/ethernet-phy.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index 6dd72faebd89..5cad653e143b 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -174,6 +174,11 @@ properties:
PHY's that have configurable TX internal delays. If this property is
present then the PHY applies the TX delay.
+ tx-rx-output-high:
+ type: boolean
+ description: |
+ Enable the 2.4v p2p differential output voltage for 10base-T1L PHYs.
+
required:
- reg
--
2.28.0.585.ge1cfff676549
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy <[email protected]>
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index 000000000000..aef949c1cfdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy <[email protected]>
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+ http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+ maxItems: 1
+
+ tx-fifo-depth:
+ description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+ enum: [ 4, 5, 6, 8 ]
+ default: 5
+
+ rx-internal-delay-ps:
+ description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+ description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+required:
+ - reg
+
+examples:
+ - |
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ tx-rx-output-high;
+ tx-fifo-depth = <5>;
+ rx-internal-delay-ps = <1>;
+ tx-internal-delay-ps = <1>;
+ };
+ };
--
2.28.0.585.ge1cfff676549
On Fri, Oct 30, 2020 at 12:29:47PM -0500, Dan Murphy wrote:
> Add entries for the 10base-T1L full and half duplex supported modes.
>
> $ ethtool eth0
> Supported ports: [ TP ]
> Supported link modes: 10baseT1L/Half 10baseT1L/Full
> Supported pause frame use: Symmetric Receive-only
> Supports auto-negotiation: Yes
> Supported FEC modes: Not reported
> Advertised link modes: 10baseT1L/Half 10baseT1L/Full
> Advertised pause frame use: No
> Advertised auto-negotiation: No
> Advertised FEC modes: Not reported
> Speed: 10Mb/s
> Duplex: Full
> Auto-negotiation: on
> Port: MII
> PHYAD: 1
> Transceiver: external
> Supports Wake-on: gs
> Wake-on: d
> SecureOn password: 00:00:00:00:00:00
> Current message level: 0x00000000 (0)
>
> Link detected: yes
>
> Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote:
> Per the 802.3cg spec the 10base T1L can operate at 2 different
> differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to
> drive that output is dependent on the PHY's on board power supply.
Hi Dan
So this property is about the board being able to support the needed
voltages? The PHY is not forced into 2.4v p2p, it just says the PHY
can operate at 2.4v and the board will not melt, blow a fuse, etc?
I actually think it is normal to specify the reverse. List the maximum
that device can do because of board restrictions. e.g.
- maximum-power-milliwatt : Maximum module power consumption
Specifies the maximum power consumption allowable by a module in the
slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W.
- max-link-speed:
If present this property specifies PCI gen for link capability. Host
drivers could add this as a strategy to avoid unnecessary operation for
unsupported link speed, for instance, trying to do training for
unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
for gen2, and '1' for gen1. Any other values are invalid.
- max-microvolt : The maximum voltage value supplied to the haptic motor.
[The unit of the voltage is a micro]
So i think this property should be
max-tx-rx-p2p = <1000>;
to limit it to 1000mv p2p because of board PSU limitations, and it is
free to do 22000mv is the property is not present.
Andrew
On Fri, Oct 30, 2020 at 12:29:49PM -0500, Dan Murphy wrote:
> The DP83TD510 is a 10M single twisted pair Ethernet PHY
>
> Signed-off-by: Dan Murphy <[email protected]>
> ---
> .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
> new file mode 100644
> index 000000000000..aef949c1cfdd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2020 Texas Instruments Incorporated
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: TI DP83TD510 ethernet PHY
> +
> +allOf:
> + - $ref: "ethernet-controller.yaml#"
> + - $ref: "ethernet-phy.yaml#"
> +
> +maintainers:
> + - Dan Murphy <[email protected]>
> +
> +description: |
> + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
> + RGMII interfaces.
> +
> + Specifications about the Ethernet PHY can be found at:
> + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + tx-fifo-depth:
> + description: |
> + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
> + depths. The valid nibble depths are 4, 5, 6 and 8.
> + enum: [ 4, 5, 6, 8 ]
> + default: 5
> +
> + rx-internal-delay-ps:
> + description: |
> + Setting this property to a non-zero number sets the RX internal delay
> + for the PHY. The internal delay for the PHY is fixed to 30ns relative
> + to receive data.
> +
> + tx-internal-delay-ps:
> + description: |
> + Setting this property to a non-zero number sets the TX internal delay
> + for the PHY. The internal delay for the PHY has a range of -4 to 4ns
> + relative to transmit data.
> +
> +required:
> + - reg
> +
I just got this feedback so I am passing it on.
Every dtbinding should have the additionalProperties set to false so
that dtbs_check can actually catch if there is a undefined property
used.
Ioana
On Fri, 30 Oct 2020 12:29:49 -0500, Dan Murphy wrote:
> The DP83TD510 is a 10M single twisted pair Ethernet PHY
>
> Signed-off-by: Dan Murphy <[email protected]>
> ---
> .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: {'$id': 'http://devicetree.org/schemas/net/ti,dp83td510.yaml#', '$schema': 'http://devicetree.org/meta-schemas/core.yaml#', 'title': 'TI DP83TD510 ethernet PHY', 'allOf': [{'$ref': 'ethernet-controller.yaml#'}, {'$ref': 'ethernet-phy.yaml#'}], 'maintainers': ['Dan Murphy <[email protected]>'], 'description': 'The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and\nRGMII interfaces.\n\nSpecifications about the Ethernet PHY can be found at:\n http://www.ti.com/lit/ds/symlink/dp83td510e.pdf\n', 'properties': {'reg': {'maxItems': 1}, 'tx-fifo-depth': {'description': 'Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble\ndepths. The valid nibble depths are 4, 5, 6 and 8.\n', 'enum': [4, 5, 6, 8], 'default': 5}, 'rx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the RX internal delay\nfor the PHY. The internal delay for the PHY is fixed to 30ns relative\nto receive data.\n'}, 'tx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the TX internal delay\nfor the PHY. The internal delay for the PHY has a range of -4 to 4ns\nrelative to transmit data.\n'}}, 'required': ['reg'], 'examples': ['mdio0 {\n #address-cells = <1>;\n #size-cells = <0>;\n ethphy0: ethernet-phy@0 {\n reg = <0>;\n tx-rx-output-high;\n tx-fifo-depth = <5>;\n rx-internal-delay-ps = <1>;\n tx-internal-delay-ps = <1>;\n };\n};\n']} is not valid under any of the given schemas
{'oneOf': [{'required': ['unevaluatedProperties']},
{'required': ['additionalProperties']}]} (Possible causes of the failure):
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: 'unevaluatedProperties' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/net/ti,dp83td510.yaml
See https://patchwork.ozlabs.org/patch/1391184
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
Andrew
On 10/30/20 2:56 PM, Andrew Lunn wrote:
> On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote:
>> Per the 802.3cg spec the 10base T1L can operate at 2 different
>> differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to
>> drive that output is dependent on the PHY's on board power supply.
> Hi Dan
>
> So this property is about the board being able to support the needed
> voltages? The PHY is not forced into 2.4v p2p, it just says the PHY
> can operate at 2.4v and the board will not melt, blow a fuse, etc?
>
> I actually think it is normal to specify the reverse. List the maximum
> that device can do because of board restrictions. e.g.
>
> - maximum-power-milliwatt : Maximum module power consumption
> Specifies the maximum power consumption allowable by a module in the
> slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W.
>
> - max-link-speed:
> If present this property specifies PCI gen for link capability. Host
> drivers could add this as a strategy to avoid unnecessary operation for
> unsupported link speed, for instance, trying to do training for
> unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
> for gen2, and '1' for gen1. Any other values are invalid.
>
> - max-microvolt : The maximum voltage value supplied to the haptic motor.
> [The unit of the voltage is a micro]
>
> So i think this property should be
>
> max-tx-rx-p2p = <1000>;
When I was re-writing the code I couldn't come up with a better property
name but I like this one.
I will implement it.
Do you have any issue with the property being in the ethernet-phy.yaml?
Dan
> Do you have any issue with the property being in the ethernet-phy.yaml?
It seems generic enough. Increasing the voltage increases the power
requirements, and maybe not all boards are capable of that.
Andrew
On Fri, Oct 30, 2020 at 08:56:55PM +0100, Andrew Lunn wrote:
> On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote:
> > Per the 802.3cg spec the 10base T1L can operate at 2 different
> > differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to
> > drive that output is dependent on the PHY's on board power supply.
>
> Hi Dan
>
> So this property is about the board being able to support the needed
> voltages? The PHY is not forced into 2.4v p2p, it just says the PHY
> can operate at 2.4v and the board will not melt, blow a fuse, etc?
>
> I actually think it is normal to specify the reverse. List the maximum
> that device can do because of board restrictions. e.g.
>
> - maximum-power-milliwatt : Maximum module power consumption
> Specifies the maximum power consumption allowable by a module in the
> slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W.
>
> - max-link-speed:
> If present this property specifies PCI gen for link capability. Host
> drivers could add this as a strategy to avoid unnecessary operation for
> unsupported link speed, for instance, trying to do training for
> unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
> for gen2, and '1' for gen1. Any other values are invalid.
>
> - max-microvolt : The maximum voltage value supplied to the haptic motor.
> [The unit of the voltage is a micro]
>
> So i think this property should be
>
> max-tx-rx-p2p = <1000>;
>
> to limit it to 1000mv p2p because of board PSU limitations, and it is
> free to do 22000mv is the property is not present.
'-microvolt' suffix please.
>
> Andrew
>
On 10/30/2020 10:29 AM, Dan Murphy wrote:
> Add entries for the 10base-T1L full and half duplex supported modes.
>
> $ ethtool eth0
> Supported ports: [ TP ]
> Supported link modes: 10baseT1L/Half 10baseT1L/Full
> Supported pause frame use: Symmetric Receive-only
> Supports auto-negotiation: Yes
> Supported FEC modes: Not reported
> Advertised link modes: 10baseT1L/Half 10baseT1L/Full
> Advertised pause frame use: No
> Advertised auto-negotiation: No
> Advertised FEC modes: Not reported
> Speed: 10Mb/s
> Duplex: Full
> Auto-negotiation: on
> Port: MII
> PHYAD: 1
> Transceiver: external
> Supports Wake-on: gs
> Wake-on: d
> SecureOn password: 00:00:00:00:00:00
> Current message level: 0x00000000 (0)
>
> Link detected: yes
>
> Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
--
Florian