The V3s/V3 has a NMI IRQ controller, which is mainly used for the AXP209
interrupt. In great wisdom, Allwinner decided to invert the enable and
pending register offsets, compared to the A20.
As a result, a specific compatible and register description is required
for the V3s. This was tested with an AXP209 on a V3 board.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
drivers/irqchip/irq-sunxi-nmi.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index a412b5d5d0fa..59e0e4612ef7 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -44,6 +44,10 @@
#define SUN7I_NMI_PENDING 0x04
#define SUN7I_NMI_ENABLE 0x08
+#define SUN8I_V3S_NMI_CTRL 0x00
+#define SUN8I_V3S_NMI_ENABLE 0x04
+#define SUN8I_V3S_NMI_PENDING 0x08
+
#define SUN9I_NMI_CTRL 0x00
#define SUN9I_NMI_ENABLE 0x04
#define SUN9I_NMI_PENDING 0x08
@@ -79,6 +83,12 @@ static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
.enable = SUN7I_NMI_ENABLE,
};
+static const struct sunxi_sc_nmi_reg_offs sun8i_v3s_reg_offs __initconst = {
+ .ctrl = SUN8I_V3S_NMI_CTRL,
+ .pend = SUN8I_V3S_NMI_PENDING,
+ .enable = SUN8I_V3S_NMI_ENABLE,
+};
+
static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
.ctrl = SUN9I_NMI_CTRL,
.pend = SUN9I_NMI_PENDING,
@@ -165,7 +175,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int ret;
-
domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
if (!domain) {
pr_err("Could not register interrupt domain.\n");
@@ -254,6 +263,13 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
}
IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
+static int __init sun8i_v3s_sc_nmi_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return sunxi_sc_nmi_irq_init(node, &sun8i_v3s_reg_offs);
+}
+IRQCHIP_DECLARE(sun8i_v3s_sc_nmi, "allwinner,sun8i-v3s-sc-nmi", sun8i_v3s_sc_nmi_irq_init);
+
static int __init sun9i_nmi_irq_init(struct device_node *node,
struct device_node *parent)
{
--
2.28.0
On Sat, Oct 31, 2020 at 07:21:33PM +0100, Paul Kocialkowski wrote:
> The V3s/V3 has a NMI IRQ controller, which is mainly used for the AXP209
> interrupt. In great wisdom, Allwinner decided to invert the enable and
> pending register offsets, compared to the A20.
>
> As a result, a specific compatible and register description is required
> for the V3s. This was tested with an AXP209 on a V3 board.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Maxime