This series adds support for the Allwinner V3-based SL631 family of
Action Cameras, starting with the IMX179 fashion.
A few fixes to V3 support are added along the way, most notably support
for the NMI IRQ controller which is necessary for the AXP209 IRQ.
Note that some patches in this series may have already been submitted
(but not yet merged) by others and are included for the series to build.
Happy reviewing!
Paul Kocialkowski (9):
ARM: sunxi: Add machine match for the Allwinner V3 SoC
ARM: dts: sun8i-v3: Add UART1 PG pins description
ARM: dts: sun8i-v3s: Add I2C1 PB pins description
dt-bindings: irq: sun7i-nmi: Add binding for the V3s NMI
irqchip/sunxi-nmi: Add support for the V3s NMI
ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller
ARM: dts: sun8i: Cleanup the Pinecube AXP209 node
dt-bindings: arm: sunxi: Add SL631 with IMX179 bindings
ARM: dts: sun8i-v3: Add support for the SL631 Action Camera with
IMX179
.../devicetree/bindings/arm/sunxi.yaml | 6 +
.../allwinner,sun7i-a20-sc-nmi.yaml | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun8i-s3-pinecube.dts | 8 +-
arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts | 12 ++
arch/arm/boot/dts/sun8i-v3-sl631.dtsi | 145 ++++++++++++++++++
arch/arm/boot/dts/sun8i-v3.dtsi | 6 +
arch/arm/boot/dts/sun8i-v3s.dtsi | 16 +-
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/irqchip/irq-sunxi-nmi.c | 18 ++-
10 files changed, 206 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts
create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631.dtsi
--
2.28.0
I2C1 can be exposed through PB pins in addition to PE pins on the V3s.
Add the device-tree description for these pins.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 0c7341676921..7b2d684aeb97 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -347,6 +347,12 @@ i2c0_pins: i2c0-pins {
function = "i2c0";
};
+ /omit-if-no-ref/
+ i2c1_pb_pins: i2c1-pb-pins {
+ pins = "PB8", "PB9";
+ function = "i2c1";
+ };
+
/omit-if-no-ref/
i2c1_pe_pins: i2c1-pe-pins {
pins = "PE21", "PE22";
--
2.28.0
UART1 is often exposed through the PG pins (usually for the debug
console) on the V3. They are not available on V3s.
Describe these pins in device-tree.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
arch/arm/boot/dts/sun8i-v3.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
index ca4672ed2e02..edf48e0471ad 100644
--- a/arch/arm/boot/dts/sun8i-v3.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3.dtsi
@@ -24,4 +24,10 @@ external_mdio: mdio@2 {
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
+
+ /omit-if-no-ref/
+ uart1_pg_pins: uart1-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
};
--
2.28.0
On Sat, Oct 31, 2020 at 07:21:31PM +0100, Paul Kocialkowski wrote:
> I2C1 can be exposed through PB pins in addition to PE pins on the V3s.
> Add the device-tree description for these pins.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
Applied, thanks!
Maxime