Add DT binding documentation and device tree nodes to enable
PCIe in J7200.
Also included a fix in J721E that fixes the maximum number of
outbound regions. (This can go in 5.11 as it doesn't impact
any of the existing use-cases).
Kishon Vijay Abraham I (8):
dt-bindings: mfd: ti,j721e-system-controller.yaml: Document
"pcie-ctrl"
dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES
arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions
.../mfd/ti,j721e-system-controller.yaml | 6 +
.../bindings/pci/ti,j721e-pci-ep.yaml | 10 +-
.../bindings/pci/ti,j721e-pci-host.yaml | 16 ++-
.../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 119 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 +-
6 files changed, 188 insertions(+), 9 deletions(-)
--
2.17.1
Add host mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3f6..ecec36c02883 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -15,8 +15,14 @@ allOf:
properties:
compatible:
- enum:
- - ti,j721e-pcie-host
+ oneOf:
+ - description: PCIe controller in J7200
+ items:
+ - const: ti,j7200-pcie-host
+ - const: ti,j721e-pcie-host
+ - description: PCIe controller in J721E
+ items:
+ - const: ti,j721e-pcie-host
reg:
maxItems: 4
@@ -48,7 +54,11 @@ properties:
const: 0x104c
device-id:
- const: 0xb00d
+ oneOf:
+ - items:
+ - const: 0xb00d
+ - items:
+ - const: 0xb00f
msi-map: true
--
2.17.1
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index ef03e7636b66..65a2e5aeb050 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -8,6 +8,7 @@
#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
/ {
chosen {
@@ -213,3 +214,25 @@
dr_mode = "otg";
maximum-speed = "high-speed";
};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 3>;
+ };
+};
--
2.17.1
Add binding documentation for "pcie-ctrl" which should be a subnode of
the system controller.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 19fcf59fd2fe..fd985794e419 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -50,6 +50,12 @@ patternProperties:
specified in
Documentation/devicetree/bindings/mux/reg-mux.txt
+ "^pcie-ctrl@[0-9a-f]+$":
+ type: object
+ description: |
+ This is the PCIe controller configuration required to configre PCIe
+ mode, lane width and speed.
+
required:
- compatible
- reg
--
2.17.1
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 7668404c178b..9892704d4b67 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -25,6 +25,14 @@
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ pcie1_ctrl: pcie-ctrl@4074 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00004074 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x4074 0x4074 0x4>;
+ };
+
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -478,6 +486,56 @@
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ cdns,max-outbound-regions = <32>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = /bits/ 16 <0x104c>;
+ device-id = /bits/ 16 <0xb00f>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <6>;
+ dma-coherent;
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 65a2e5aeb050..174a55a18522 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
@@ -236,3 +237,17 @@
resets = <&serdes_wiz0 3>;
};
};
+
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie1_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
--
2.17.1
Add dt node for the single instance of WIZ and SERDES module
shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..7668404c178b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -417,6 +417,67 @@
dma-coherent;
};
+ serdes_refclk: serdes_refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 292 85>;
+ assigned-clock-parents = <&k3_clks 292 89>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
PCIe controller in J721E supports a maximum of 32 outbound regions.
commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
nodes") incorrectly added maximum number of outbound regions to 16. Fix
it here.
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e2a96b2c423c..61b533130ed1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -652,7 +652,7 @@
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -701,7 +701,7 @@
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -750,7 +750,7 @@
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -799,7 +799,7 @@
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
--
2.17.1
Add PCIe EP mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 3ae3e1a2d4b0..da8c5b892104 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -15,8 +15,14 @@ allOf:
properties:
compatible:
- enum:
- - ti,j721e-pcie-ep
+ oneOf:
+ - description: PCIe EP controller in J7200
+ items:
+ - const: ti,j7200-pcie-ep
+ - const: ti,j721e-pcie-ep
+ - description: PCIe EP controller in J721E
+ items:
+ - const: ti,j721e-pcie-ep
reg:
maxItems: 4
--
2.17.1
On 15:41-20201102, Kishon Vijay Abraham I wrote:
> PCIe controller in J721E supports a maximum of 32 outbound regions.
> commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
> nodes") incorrectly added maximum number of outbound regions to 16. Fix
> it here.
>
> Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index e2a96b2c423c..61b533130ed1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -652,7 +652,7 @@
> power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 239 1>;
> clock-names = "fck";
> - cdns,max-outbound-regions = <16>;
> + cdns,max-outbound-regions = <32>;
> max-functions = /bits/ 8 <6>;
> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
> dma-coherent;
> @@ -701,7 +701,7 @@
> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 240 1>;
> clock-names = "fck";
> - cdns,max-outbound-regions = <16>;
> + cdns,max-outbound-regions = <32>;
> max-functions = /bits/ 8 <6>;
> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
> dma-coherent;
> @@ -750,7 +750,7 @@
> power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 241 1>;
> clock-names = "fck";
> - cdns,max-outbound-regions = <16>;
> + cdns,max-outbound-regions = <32>;
> max-functions = /bits/ 8 <6>;
> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
> dma-coherent;
> @@ -799,7 +799,7 @@
> power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 242 1>;
> clock-names = "fck";
> - cdns,max-outbound-regions = <16>;
> + cdns,max-outbound-regions = <32>;
> max-functions = /bits/ 8 <6>;
> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
> dma-coherent;
> --
> 2.17.1
>
Does this need to be part of this series? If NOT, please pull this out
and repost so that it can be independently picked up since there is no
dependency on the bindings or any part of this series?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Nishanth,
On 02/11/20 10:11 pm, Nishanth Menon wrote:
> On 15:41-20201102, Kishon Vijay Abraham I wrote:
>> PCIe controller in J721E supports a maximum of 32 outbound regions.
>> commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
>> nodes") incorrectly added maximum number of outbound regions to 16. Fix
>> it here.
>>
>> Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index e2a96b2c423c..61b533130ed1 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -652,7 +652,7 @@
>> power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 239 1>;
>> clock-names = "fck";
>> - cdns,max-outbound-regions = <16>;
>> + cdns,max-outbound-regions = <32>;
>> max-functions = /bits/ 8 <6>;
>> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>> dma-coherent;
>> @@ -701,7 +701,7 @@
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 240 1>;
>> clock-names = "fck";
>> - cdns,max-outbound-regions = <16>;
>> + cdns,max-outbound-regions = <32>;
>> max-functions = /bits/ 8 <6>;
>> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>> dma-coherent;
>> @@ -750,7 +750,7 @@
>> power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 241 1>;
>> clock-names = "fck";
>> - cdns,max-outbound-regions = <16>;
>> + cdns,max-outbound-regions = <32>;
>> max-functions = /bits/ 8 <6>;
>> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>> dma-coherent;
>> @@ -799,7 +799,7 @@
>> power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 242 1>;
>> clock-names = "fck";
>> - cdns,max-outbound-regions = <16>;
>> + cdns,max-outbound-regions = <32>;
>> max-functions = /bits/ 8 <6>;
>> max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
>> dma-coherent;
>> --
>> 2.17.1
>>
>
> Does this need to be part of this series? If NOT, please pull this out
> and repost so that it can be independently picked up since there is no
> dependency on the bindings or any part of this series?
>
Sure, okay!
Regards
Kishon
On Mon, Nov 02, 2020 at 03:41:47PM +0530, Kishon Vijay Abraham I wrote:
> Add binding documentation for "pcie-ctrl" which should be a subnode of
> the system controller.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index 19fcf59fd2fe..fd985794e419 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -50,6 +50,12 @@ patternProperties:
> specified in
> Documentation/devicetree/bindings/mux/reg-mux.txt
>
> + "^pcie-ctrl@[0-9a-f]+$":
Unit address, so it should have 'reg' too?
You don't need a node if there aren't any properties.
> + type: object
> + description: |
> + This is the PCIe controller configuration required to configre PCIe
> + mode, lane width and speed.
> +
> required:
> - compatible
> - reg
> --
> 2.17.1
>
On Mon, 02 Nov 2020 15:41:48 +0530, Kishon Vijay Abraham I wrote:
> Add host mode dt-bindings for TI's J7200 SoC.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> .../bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, Nov 02, 2020 at 10:41:37AM -0600, Nishanth Menon wrote:
> On 15:41-20201102, Kishon Vijay Abraham I wrote:
> > PCIe controller in J721E supports a maximum of 32 outbound regions.
> > commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
> > nodes") incorrectly added maximum number of outbound regions to 16. Fix
> > it here.
> >
> > Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
> > Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> > ---
> > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> > index e2a96b2c423c..61b533130ed1 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> > @@ -652,7 +652,7 @@
> > power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> > clocks = <&k3_clks 239 1>;
> > clock-names = "fck";
> > - cdns,max-outbound-regions = <16>;
> > + cdns,max-outbound-regions = <32>;
Can this be made detectable instead? Write to region registers and check
the write sticks? I'm doing this for the DWC controller.
Or make the property optional with the default being the max (32).
Rob
On Mon, 02 Nov 2020 15:41:49 +0530, Kishon Vijay Abraham I wrote:
> Add PCIe EP mode dt-bindings for TI's J7200 SoC.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
Hi Rob,
On 05/11/20 10:23 pm, Rob Herring wrote:
> On Mon, Nov 02, 2020 at 10:41:37AM -0600, Nishanth Menon wrote:
>> On 15:41-20201102, Kishon Vijay Abraham I wrote:
>>> PCIe controller in J721E supports a maximum of 32 outbound regions.
>>> commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
>>> nodes") incorrectly added maximum number of outbound regions to 16. Fix
>>> it here.
>>>
>>> Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
>>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> index e2a96b2c423c..61b533130ed1 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -652,7 +652,7 @@
>>> power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>> clocks = <&k3_clks 239 1>;
>>> clock-names = "fck";
>>> - cdns,max-outbound-regions = <16>;
>>> + cdns,max-outbound-regions = <32>;
>
> Can this be made detectable instead? Write to region registers and check
> the write sticks? I'm doing this for the DWC controller.
>
> Or make the property optional with the default being the max (32).
okay, I'll make this an optional property and send a patch which removes
cdns,max-outbound-regions in k3-j721e-main.dtsi.
Thanks,
Kishon
Hi Rob,
On 05/11/20 10:24 pm, Rob Herring wrote:
> On Mon, Nov 02, 2020 at 03:41:47PM +0530, Kishon Vijay Abraham I wrote:
>> Add binding documentation for "pcie-ctrl" which should be a subnode of
>> the system controller.
>>
>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>> ---
>> .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> index 19fcf59fd2fe..fd985794e419 100644
>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> @@ -50,6 +50,12 @@ patternProperties:
>> specified in
>> Documentation/devicetree/bindings/mux/reg-mux.txt
>>
>> + "^pcie-ctrl@[0-9a-f]+$":
>
> Unit address, so it should have 'reg' too?
>
> You don't need a node if there aren't any properties.
The subnodes are again a syscon node. I'll fix this up in the next revision.
Thank You,
Kishon