Series includes 2 DT fixes
1) Fix the maximum number of outbound regions
2) Re-name link name as "phy" as commented by Rob in a different patch
[1] and the YAML schema posted in lkml will check the subnode as
"phy" [2]
[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus
[2] -> http://lore.kernel.org/r/[email protected]
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions
arm64: dts: ti: k3-j721e-common-proc-board: Re-name link name as "phy"
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++----
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
--
2.17.1
PCIe controller in J721E supports a maximum of 32 outbound regions.
commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
nodes") incorrectly added maximum number of outbound regions to 16. Fix
it here.
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e2a96b2c423c..61b533130ed1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -652,7 +652,7 @@
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -701,7 +701,7 @@
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -750,7 +750,7 @@
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -799,7 +799,7 @@
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
+ cdns,max-outbound-regions = <32>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
--
2.17.1
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy'. Re-name
subnodes of serdes in J721E to 'phy'.
Link: http://lore.kernel.org/r/20200909203631.GA3026331@bogus
Link: http://lore.kernel.org/r/[email protected]
Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 52e121155563..e837614d8d88 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -325,7 +325,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -561,7 +561,7 @@
};
&serdes0 {
- serdes0_pcie_link: link@0 {
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -571,7 +571,7 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -581,7 +581,7 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
--
2.17.1