On Layerscape SoCs which feature the FlexSPI controller there is
a single register which can control the divider value. The base
frequency is the platform PLL.
Right now the LS1028A and the LX2160A aren't able to switch the
SCK frequency on the FlexSPI interface. Add a new clock driver
which operate on said register.
Michael Walle (5):
clk: divider: add devm_clk_hw_register_divider_table()
dt-bindings: clock: document the fsl-flexspi-clk driver
clk: fsl-flexspi: new driver
arm64: dts: ls1028a: fix FlexSPI clock
arm64: dts: lx2160a: fix FlexSPI clock
.../bindings/clock/fsl,flexspi-clock.yaml | 55 +++++++++
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 ++-
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 ++-
drivers/clk/Kconfig | 8 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-divider.c | 34 ++++++
drivers/clk/clk-fsl-flexspi.c | 106 ++++++++++++++++++
include/linux/clk-provider.h | 27 +++++
8 files changed, 257 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
create mode 100644 drivers/clk/clk-fsl-flexspi.c
--
2.20.1
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v1:
- none
.../bindings/clock/fsl,flexspi-clock.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
new file mode 100644
index 000000000000..1fa390ee7b9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale FlexSPI clock driver for Layerscape SoCs
+
+maintainers:
+ - Michael Walle <[email protected]>
+
+description:
+ The Freescale Layerscape SoCs have a special FlexSPI clock which is
+ derived from the platform PLL.
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-flexspi-clk
+ - fsl,lx2160a-flexspi-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ dcfg {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&parentclk>;
+ clock-output-names = "fspi_clk";
+ };
+ };
--
2.20.1