2020-11-05 23:21:39

by Coiby Xu

Subject: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

The correct way to disable debounce filter is to clear bit 5 and 6
of the register.

Cc: Hans de Goede <[email protected]>
Link: https://lore.kernel.org/linux-gpio/[email protected]/
Signed-off-by: Coiby Xu <[email protected]>
---
drivers/pinctrl/pinctrl-amd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 9a760f5cd7ed..d6b2b4bd337c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= BIT(DB_TMR_LARGE_OFF);
} else {
- pin_reg &= ~DB_CNTRl_MASK;
+ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
ret = -EINVAL;
}
} else {
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg &= ~DB_TMR_OUT_MASK;
- pin_reg &= ~DB_CNTRl_MASK;
+ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
--
2.28.0

2020-11-09 13:53:53

by Hans de Goede

Subject: Re: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

Hi,

On 11/6/20 12:19 AM, Coiby Xu wrote:
> The correct way to disable debounce filter is to clear bit 5 and 6
> of the register.
>
> Cc: Hans de Goede <[email protected]>
> Link: https://lore.kernel.org/linux-gpio/[email protected]/
> Signed-off-by: Coiby Xu <[email protected]>

Thanks, patch looks good to me:

Reviewed-by: Hans de Goede <[email protected]>

Regards,

Hans

> ---
> drivers/pinctrl/pinctrl-amd.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index 9a760f5cd7ed..d6b2b4bd337c 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
> pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
> pin_reg |= BIT(DB_TMR_LARGE_OFF);
> } else {
> - pin_reg &= ~DB_CNTRl_MASK;
> + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
> ret = -EINVAL;
> }
> } else {
> pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
> pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
> pin_reg &= ~DB_TMR_OUT_MASK;
> - pin_reg &= ~DB_CNTRl_MASK;
> + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
> }
> writel(pin_reg, gpio_dev->base + offset * 4);
> raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
>

2020-11-10 13:21:39

by Linus Walleij

Subject: Re: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

On Fri, Nov 6, 2020 at 12:19 AM Coiby Xu <[email protected]> wrote:

> The correct way to disable debounce filter is to clear bit 5 and 6
> of the register.
>
> Cc: Hans de Goede <[email protected]>
> Link: https://lore.kernel.org/linux-gpio/[email protected]/
> Signed-off-by: Coiby Xu <[email protected]>

This patch applied for fixes and tagged for stable.

Yours,
Linus Walleij