Add binding doc for fsl,spba-bus.
Signed-off-by: Adam Ford <[email protected]>
---
V4: Correct errors in YAML
V3: New to series
.../devicetree/bindings/bus/fsl,spba-bus.yaml | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
new file mode 100644
index 000000000000..d1037acd2734
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Shared Peripherals Bus Interface
+
+maintainers:
+ - Shawn Guo <[email protected]>
+
+description: |
+ A simple bus enabling access to shared peripherals.
+
+ The "spba-bus" follows the "simple-bus" set of properties, as
+ specified in the Devicetree Specification. It is an extension of
+ "simple-bus" because the SDMA controller uses this compatible flag to
+ determine which peripherals are available to it and the range over which
+ the SDMA can access. There are no special clocks for the bus, because
+ the SDMA controller itself has its interrupt, and clock assignments.
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: fsl,spba-bus
+ required:
+ - compatible
+
+properties:
+ $nodename:
+ pattern: "^bus(@[0-9a-f]+)?$"
+
+ compatible:
+ contains:
+ const: fsl,spba-bus
+ items:
+ - const: fsl,spba-bus
+ - const: simple-bus
+
+ '#address-cells':
+ enum: [ 1, 2 ]
+
+ '#size-cells':
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+
+additionalProperties: true
+
+type: object
+
+examples:
+ - |
+ bus {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
--
2.25.1
The i.MX8M Nano has several SAI nodes available to it.
Enable them.
Signed-off-by: Adam Ford <[email protected]>
---
V4: No Change
V3: No Change
V2: No Change
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 72 +++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 61560c083300..6ea0d43a78a3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -260,6 +260,78 @@ spba: bus@30000000 {
reg = <0x30000000 0x100000>;
ranges;
+ sai2: sai@30020000 {
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30020000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
+ <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_SAI2_ROOT>,
+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai@30030000 {
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30030000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
+ <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_SAI3_ROOT>,
+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai5: sai@30050000 {
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30050000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
+ <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_SAI5_ROOT>,
+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ fsl,shared-interrupt;
+ fsl,dataline = <0 0xf 0xf>;
+ status = "disabled";
+ };
+
+ sai6: sai@30060000 {
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30060000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
+ <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_SAI6_ROOT>,
+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai7: sai@300b0000 {
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x300b0000 0x10000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
+ <&clk IMX8MN_CLK_DUMMY>,
+ <&clk IMX8MN_CLK_SAI7_ROOT>,
+ <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
easrc: easrc@300c0000 {
compatible = "fsl,imx8mn-easrc";
reg = <0x300c0000 0x10000>;
--
2.25.1
The driver exists for the Enhanced Asynchronous Sample Rate Converter
(EASRC) Controller, but there isn't a device tree entry for it.
On the vendor kernel, they put this on a spba-bus for SDMA support.
Add the node for the spba-bus with the easrc node inside.
Signed-off-by: Adam Ford <[email protected]>
---
V4: No change
V3: Change spba-bus@30000000 to spba: bus@30000000
V2: Make the DT node more in-line with the dt binding and remove
vendor customizations that are not applicable.
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a06d2a6268e6..61560c083300 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -253,6 +253,34 @@ aips1: bus@30000000 {
#size-cells = <1>;
ranges;
+ spba: bus@30000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x100000>;
+ ranges;
+
+ easrc: easrc@300c0000 {
+ compatible = "fsl,imx8mn-easrc";
+ reg = <0x300c0000 0x10000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
+ clock-names = "mem";
+ dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
+ <&sdma2 18 23 0> , <&sdma2 19 23 0>,
+ <&sdma2 20 23 0> , <&sdma2 21 23 0>,
+ <&sdma2 22 23 0> , <&sdma2 23 23 0>;
+ dma-names = "ctx0_rx", "ctx0_tx",
+ "ctx1_rx", "ctx1_tx",
+ "ctx2_rx", "ctx2_tx",
+ "ctx3_rx", "ctx3_tx";
+ firmware-name = "imx/easrc/easrc-imx8mn.bin";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-format = <2>;
+ status = "disabled";
+ };
+ };
+
gpio1: gpio@30200000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
--
2.25.1
The i.MX8M Nano has supports the MICFIL digital interface.
It's a 16-bit audio signal from a PDM microphone bitstream.
The driver is already in the kernel, but the node is missing.
Add the micfil node.
Signed-off-by: Adam Ford <[email protected]>
---
V4: No Change
V3: No Change
V2: Change micfil@30080000 to audio-controller@30080000
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 6ea0d43a78a3..aa3f1eb391bd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -318,6 +318,25 @@ sai6: sai@30060000 {
status = "disabled";
};
+ micfil: audio-controller@30080000 {
+ compatible = "fsl,imx8mm-micfil";
+ reg = <0x30080000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_PDM_IPG>,
+ <&clk IMX8MN_CLK_PDM_ROOT>,
+ <&clk IMX8MN_AUDIO_PLL1_OUT>,
+ <&clk IMX8MN_AUDIO_PLL2_OUT>,
+ <&clk IMX8MN_CLK_EXT3>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "pll11k", "clkext3";
+ dmas = <&sdma2 24 25 0x80000000>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
sai7: sai@300b0000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
--
2.25.1
The i.MX8M Nano can support SPDIF which is compatible to the
IP used on the i.MX35.
Add the node.
Signed-off-by: Adam Ford <[email protected]>
---
V4: No Change
V3: No Change
V2: No Change
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index aa3f1eb391bd..ee1790230490 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -337,6 +337,30 @@ micfil: audio-controller@30080000 {
status = "disabled";
};
+ spdif1: spdif@30090000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x30090000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
+ <&clk IMX8MN_CLK_24M>, /* rxtx0 */
+ <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MN_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
sai7: sai@300b0000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
--
2.25.1
On Sat, 07 Nov 2020 05:58:04 -0600, Adam Ford wrote:
> Add binding doc for fsl,spba-bus.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> V4: Correct errors in YAML
> V3: New to series
>
> .../devicetree/bindings/bus/fsl,spba-bus.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml: properties:items: [{'const': 'fsl,spba-bus'}, {'const': 'simple-bus'}] is not of type 'object', 'boolean'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml: Additional properties are not allowed ('type' was unexpected)
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml: properties: {'enum': ['$ref', 'additionalItems', 'additionalProperties', 'allOf', 'anyOf', 'const', 'contains', 'default', 'dependencies', 'deprecated', 'description', 'else', 'enum', 'if', 'items', 'maxItems', 'maximum', 'minItems', 'minimum', 'multipleOf', 'not', 'oneOf', 'pattern', 'patternProperties', 'properties', 'propertyNames', 'required', 'then', 'unevaluatedProperties']} is not allowed for 'items'
./Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml: ignoring, error in schema: properties: items
warning: no schema found in file: ./Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
See https://patchwork.ozlabs.org/patch/1396117
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Sat, Nov 7, 2020 at 5:58 AM Adam Ford <[email protected]> wrote:
>
> The driver exists for the Enhanced Asynchronous Sample Rate Converter
> (EASRC) Controller, but there isn't a device tree entry for it.
>
> On the vendor kernel, they put this on a spba-bus for SDMA support.
>
> Add the node for the spba-bus with the easrc node inside.
>
> Signed-off-by: Adam Ford <[email protected]>
Shawn,
I split the dt-binding into a separate patch since I was struggling
with checking the yaml syntax. Rob helped me find the proper branch
to use. I hope it goes through this time.
Do you have any comments on the rest of the series? I would like to
fix them if you have any concerns so I can resend if/when the
dt-binding is accepted.
thanks,
adam
> ---
> V4: No change
> V3: Change spba-bus@30000000 to spba: bus@30000000
> V2: Make the DT node more in-line with the dt binding and remove
> vendor customizations that are not applicable.
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index a06d2a6268e6..61560c083300 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -253,6 +253,34 @@ aips1: bus@30000000 {
> #size-cells = <1>;
> ranges;
>
> + spba: bus@30000000 {
> + compatible = "fsl,spba-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x30000000 0x100000>;
> + ranges;
> +
> + easrc: easrc@300c0000 {
> + compatible = "fsl,imx8mn-easrc";
> + reg = <0x300c0000 0x10000>;
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
> + clock-names = "mem";
> + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
> + <&sdma2 18 23 0> , <&sdma2 19 23 0>,
> + <&sdma2 20 23 0> , <&sdma2 21 23 0>,
> + <&sdma2 22 23 0> , <&sdma2 23 23 0>;
> + dma-names = "ctx0_rx", "ctx0_tx",
> + "ctx1_rx", "ctx1_tx",
> + "ctx2_rx", "ctx2_tx",
> + "ctx3_rx", "ctx3_tx";
> + firmware-name = "imx/easrc/easrc-imx8mn.bin";
> + fsl,asrc-rate = <8000>;
> + fsl,asrc-format = <2>;
> + status = "disabled";
> + };
> + };
> +
> gpio1: gpio@30200000 {
> compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
> reg = <0x30200000 0x10000>;
> --
> 2.25.1
>
On Mon, Nov 30, 2020 at 06:08:25PM -0600, Adam Ford wrote:
> On Wed, Nov 18, 2020 at 5:13 PM Adam Ford <[email protected]> wrote:
> >
> > On Sat, Nov 7, 2020 at 5:58 AM Adam Ford <[email protected]> wrote:
> > >
> > > The driver exists for the Enhanced Asynchronous Sample Rate Converter
> > > (EASRC) Controller, but there isn't a device tree entry for it.
> > >
> > > On the vendor kernel, they put this on a spba-bus for SDMA support.
> > >
> > > Add the node for the spba-bus with the easrc node inside.
> > >
> > > Signed-off-by: Adam Ford <[email protected]>
> >
> > Shawn,
> >
> > I split the dt-binding into a separate patch since I was struggling
> > with checking the yaml syntax. Rob helped me find the proper branch
> > to use. I hope it goes through this time.
> >
> > Do you have any comments on the rest of the series? I would like to
> > fix them if you have any concerns so I can resend if/when the
> > dt-binding is accepted.
>
> Shawn,
>
> The dt-binding was accepted per [1]. How do you want me to proceed
> for the rest of the series? I can resend the other parts without the
> dt-binding if you like.
Applied 4 DTS patches, thanks.
On Wed, Nov 18, 2020 at 5:13 PM Adam Ford <[email protected]> wrote:
>
> On Sat, Nov 7, 2020 at 5:58 AM Adam Ford <[email protected]> wrote:
> >
> > The driver exists for the Enhanced Asynchronous Sample Rate Converter
> > (EASRC) Controller, but there isn't a device tree entry for it.
> >
> > On the vendor kernel, they put this on a spba-bus for SDMA support.
> >
> > Add the node for the spba-bus with the easrc node inside.
> >
> > Signed-off-by: Adam Ford <[email protected]>
>
> Shawn,
>
> I split the dt-binding into a separate patch since I was struggling
> with checking the yaml syntax. Rob helped me find the proper branch
> to use. I hope it goes through this time.
>
> Do you have any comments on the rest of the series? I would like to
> fix them if you have any concerns so I can resend if/when the
> dt-binding is accepted.
Shawn,
The dt-binding was accepted per [1]. How do you want me to proceed
for the rest of the series? I can resend the other parts without the
dt-binding if you like.
thanks,
adam
[1] - https://lkml.org/lkml/2020/11/30/1211
>
> thanks,
>
> adam
>
> > ---
> > V4: No change
> > V3: Change spba-bus@30000000 to spba: bus@30000000
> > V2: Make the DT node more in-line with the dt binding and remove
> > vendor customizations that are not applicable.
> > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > index a06d2a6268e6..61560c083300 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > @@ -253,6 +253,34 @@ aips1: bus@30000000 {
> > #size-cells = <1>;
> > ranges;
> >
> > + spba: bus@30000000 {
> > + compatible = "fsl,spba-bus", "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + reg = <0x30000000 0x100000>;
> > + ranges;
> > +
> > + easrc: easrc@300c0000 {
> > + compatible = "fsl,imx8mn-easrc";
> > + reg = <0x300c0000 0x10000>;
> > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
> > + clock-names = "mem";
> > + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
> > + <&sdma2 18 23 0> , <&sdma2 19 23 0>,
> > + <&sdma2 20 23 0> , <&sdma2 21 23 0>,
> > + <&sdma2 22 23 0> , <&sdma2 23 23 0>;
> > + dma-names = "ctx0_rx", "ctx0_tx",
> > + "ctx1_rx", "ctx1_tx",
> > + "ctx2_rx", "ctx2_tx",
> > + "ctx3_rx", "ctx3_tx";
> > + firmware-name = "imx/easrc/easrc-imx8mn.bin";
> > + fsl,asrc-rate = <8000>;
> > + fsl,asrc-format = <2>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > gpio1: gpio@30200000 {
> > compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
> > reg = <0x30200000 0x10000>;
> > --
> > 2.25.1
> >