Now that we have a proper driver for the FlexSPI interface use it. This
will fix SCK frequency switching on Layerscape SoCs.
Signed-off-by: Michael Walle <[email protected]>
---
Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But
this patch is marked as RFC nonetheless, because there is too much
difference in the clock tree between LS1028A and LX2160A. It would be nice
if someone could test it and add a Tested-by.
Changes since v2:
- none
Changes since v1:
- none
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 0a54a54ec770..130de5f7ff5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -661,9 +661,20 @@
};
dcfg: syscon@1e00000 {
- compatible = "fsl,lx2160a-dcfg", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
reg = <0x0 0x1e00000 0x0 0x10000>;
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
little-endian;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,lx2160a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&clockgen 4 0>;
+ clock-output-names = "fspi_clk";
+ };
};
tmu: tmu@1f80000 {
@@ -778,7 +789,7 @@
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 3>, <&fspi_clk>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
--
2.20.1
On Sun, Nov 08, 2020 at 07:51:13PM +0100, Michael Walle wrote:
> Now that we have a proper driver for the FlexSPI interface use it. This
> will fix SCK frequency switching on Layerscape SoCs.
>
> Signed-off-by: Michael Walle <[email protected]>
> ---
> Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But
> this patch is marked as RFC nonetheless, because there is too much
> difference in the clock tree between LS1028A and LX2160A. It would be nice
> if someone could test it and add a Tested-by.
You want someone to probe the SCK frequency? I expect that if frequency
switching works on LS1028A, and the lx2160a_flexspi_divs table is
correct (which, based on the documentation for FlexSPICR1[FlexSPI_CLK_DIV],
it is), then it would work on LX2160A too?
Is there a simple test that can be made in order to trivially determine
whether the frequencies are correct?
Am 2020-11-08 22:21, schrieb Vladimir Oltean:
> On Sun, Nov 08, 2020 at 07:51:13PM +0100, Michael Walle wrote:
>> Now that we have a proper driver for the FlexSPI interface use it.
>> This
>> will fix SCK frequency switching on Layerscape SoCs.
>>
>> Signed-off-by: Michael Walle <[email protected]>
>> ---
>> Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB.
>> But
>> this patch is marked as RFC nonetheless, because there is too much
>> difference in the clock tree between LS1028A and LX2160A. It would be
>> nice
>> if someone could test it and add a Tested-by.
>
> You want someone to probe the SCK frequency?
No not really, just a thorough test.
> I expect that if frequency
> switching works on LS1028A, and the lx2160a_flexspi_divs table is
> correct (which, based on the documentation for
> FlexSPICR1[FlexSPI_CLK_DIV],
> it is), then it would work on LX2160A too?
The switching should work. Finding out wether it is correct can be
checked
by reading the raw register value, i.e. 01E0_0900h. But the parent clock
is
what is bothering me a little. Getting that wrong would lead to a wrong
SCK
output frequency albeit the divider is set to a correct value.
> Is there a simple test that can be made in order to trivially determine
> whether the frequencies are correct?
We already found out that there seems to be kind of a saturation with
higher frequencies, i.e. octal SPI bus is capable of a much higher
throughput but we only achieve 50MB/s. I'd have expected a much higher
datarate (I mean it is advertised as high performance and it uses a 8
bit
wide databus..). But anyway, it might make sense to go the other way,
i.e.
find out the max datathroughput at lower frequencies and look if it
makes
sense. Assuming no DDR, the throughput should be around your frequency.
For
example, having 4 MHz should result in 4MB/s data throughput.
OTOH we already saw that after linux booted - with the current device
tree
which has a setting of 50MHz max SCK frequency - the programmed divider
by
my driver is the same as the former setting (0x13, div-by-32); so this
series
doesn't change the SCK frequency.
-michael