Series support Engicam PX30.Core SOM changes along with C.TOUCH
Open Frame 10.1" board.
All respetive LCD panels are in Mainline already.
thanks,
Jagan.
Jagan Teki (7):
arm64: dts: rockchip: px30-enagicam: Enable USB Host, OTG
arm64: dts: rockchip: px30-engicam-edimm2.2: Enable LVDS panel
dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
arm64: defconfig: Enable ROCKCHIP_LVDS
arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY
arm64: defconfig: Enable USB_SERIAL_CP210X
Suniel Mahesh (2):
arm64: dts: rockchip: px30-engicam: Add WiFi support
arm64: dts: rockchip: px30-engicam: Add BT support
.../devicetree/bindings/arm/rockchip.yaml | 6 ++
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/px30-engicam-common.dtsi | 85 +++++++++++++++++++
.../dts/rockchip/px30-engicam-ctouch2.dtsi | 22 +++++
.../dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 +++++++++++++
.../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++++++++++++++
.../px30-engicam-px30-core-edimm2.2.dts | 22 +++++
.../dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++
arch/arm64/configs/defconfig | 3 +
9 files changed, 280 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts
--
2.25.1
Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS
panel from yes-optoelectronics.
This patch adds panel enablement nodes on respective dts(i) files.
Signed-off-by: Jagan Teki <[email protected]>
---
.../dts/rockchip/px30-engicam-common.dtsi | 4 ++
.../dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 +++++++++++++++++++
.../dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++
3 files changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index fbbdbb0a40af..8fdd7ff2fdf9 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -25,6 +25,10 @@ &gmac {
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sdmmc {
cap-sd-highspeed;
card-detect-delay = <800>;
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
index cb00988953e9..449b8eb6454e 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
@@ -5,3 +5,62 @@
*/
#include "px30-engicam-common.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+ power-supply = <&vcc3v3_lcd>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
index db22f776c68f..cdacd3483600 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
@@ -192,6 +192,11 @@ regulator-state-mem {
};
};
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3_lcd";
+ };
+
vcc5v0_host: SWITCH_REG2 {
regulator-name = "vcc5v0_host";
regulator-always-on;
--
2.25.1
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
Add bindings for it.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 37fd456170d2..ef4544ad6f82 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -76,6 +76,12 @@ properties:
- const: engicam,px30-core
- const: rockchip,px30
+ - description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame
+ items:
+ - const: engicam,px30-core-ctouch2-of10
+ - const: engicam,px30-core
+ - const: rockchip,px30
+
- description: Engicam PX30.Core EDIMM2.2 Starter Kit
items:
- const: engicam,px30-core-edimm2.2
--
2.25.1
dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
Add support for it.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++++++++++++++++
2 files changed, 78 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 5a53979b7057..1ab55a124a87 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts
new file mode 100644
index 000000000000..47aa30505a42
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+ "rockchip,px30";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ panel {
+ compatible = "ampire,am-1280800n3tzqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <&vcc3v3_lcd>;
+ data-mapping = "vesa-24";
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
--
2.25.1
Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host
and OTG ports.
Add support to enable USB on these kits while mounting
px30-core SOM.
Signed-off-by: Jagan Teki <[email protected]>
---
.../dts/rockchip/px30-engicam-common.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index bd5bde989e8d..fbbdbb0a40af 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -33,7 +33,31 @@ &sdmmc {
status = "okay";
};
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
In order to work LDVS, DSI in mainline tree for Rockchip based
hardware platforms, the associated PHY driver has to enable
in default defconfig.
Enable rockchip DSI phy driver.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 947e14d6ecae..8d205f0a3a0a 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1018,6 +1018,7 @@ CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
CONFIG_PHY_ROCKCHIP_PCIE=m
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_UNIPHIER_USB2=y
--
2.25.1
Some hardware platforms required CP20x USB to Serial converter
in order to work onboard functionalities like Bluetooth.
An example of such a platform is from Engicam's PX30 (ARM64).
Mark it as module in defconfig.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8d205f0a3a0a..14bed4a41bf0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -758,6 +758,7 @@ CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_ISP1760=y
CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_HSIC_USB3503=y
CONFIG_NOP_USB_XCEIV=y
--
2.25.1
Now, some of the rockchip hardware platforms do enable
lvds in mainline tree.
So, enable Rockchip LVDS driver via default defconfig.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a17d84ad517a..947e14d6ecae 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -646,6 +646,7 @@ CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_DW_HDMI=m
CONFIG_DRM_SUN4I=m
--
2.25.1
From: Suniel Mahesh <[email protected]>
Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the SDIO bus.
The SDIO power sequnce is connacted with exteernal 32KHz oscillator
and it require 3V3 regulator input.
This patch adds WiFi enablement nodes for these respective boards.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Suniel Mahesh <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
.../dts/rockchip/px30-engicam-common.dtsi | 45 +++++++++++++++++++
.../dts/rockchip/px30-engicam-ctouch2.dtsi | 12 +++++
.../px30-engicam-px30-core-edimm2.2.dts | 12 +++++
3 files changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index 8fdd7ff2fdf9..92681ccf50f1 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -14,6 +14,51 @@ vcc5v0_sys: vcc5v0-sys {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+
+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rf_aux_mod";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&xin32k>;
+ clock-names = "ext_clock";
+ post-power-on-delay-ms = <80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
};
&gmac {
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
index 58425b1e559f..d5708779c285 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
@@ -6,3 +6,15 @@
*/
#include "px30-engicam-common.dtsi"
+
+&pinctrl {
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
index e54d1e480daa..913444548b59 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
@@ -19,3 +19,15 @@ chosen {
stdout-path = "serial2:115200n8";
};
};
+
+&pinctrl {
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
--
2.25.1
From: Suniel Mahesh <[email protected]>
Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the UART bus.
UART bus on the design routed via USB to UART CP20x bridge. This
bridge powered from 3V3 regualtor gpio.
This patch adds BT enablement nodes for these respective boards.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Suniel Mahesh <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
.../arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++
.../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++
.../dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++
3 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index 92681ccf50f1..eb2be7893863 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -40,6 +40,18 @@ sdio_pwrseq: sdio-pwrseq {
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
};
+
+ vcc3v3_btreg: vcc3v3-btreg {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable_h>;
+ regulator-name = "btreg-gpio-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ states = <3300000 0x0>;
+ };
};
&sdio {
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
index d5708779c285..bf10a3d29fca 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
@@ -8,6 +8,12 @@
#include "px30-engicam-common.dtsi"
&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -18,3 +24,7 @@ wifi_enable_h: wifi-enable-h {
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
index 913444548b59..d759478e1c84 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
@@ -21,6 +21,12 @@ chosen {
};
&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -31,3 +37,7 @@ wifi_enable_h: wifi-enable-h {
&sdio_pwrseq {
reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};
--
2.25.1
On Mon, 9 Nov 2020 23:40:08 +0530, Jagan Teki wrote:
> Series support Engicam PX30.Core SOM changes along with C.TOUCH
> Open Frame 10.1" board.
>
> All respetive LCD panels are in Mainline already.
>
> thanks,
> Jagan.
>
> [...]
Applied, thanks!
[1/9] arm64: dts: rockchip: px30-enagicam: Enable USB Host, OTG
commit: 4548ea027c900f1e0f07a292b8e10dc3d2725f44
[2/9] arm64: dts: rockchip: px30-engicam-edimm2.2: Enable LVDS panel
commit: 87761edeb2cd90b8251f269eb52c4b48152aace8
[3/9] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
commit: 23708d46101b5d5538c88b84b764d0ed9d8957ca
[4/9] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
commit: 0e418423be1c824b2cda37fd00528f62231cd219
[5/9] arm64: dts: rockchip: px30-engicam: Add WiFi support
commit: 93a4e7d12468b0ab46796f3ed8dc5838dc7f63bc
[6/9] arm64: dts: rockchip: px30-engicam: Add BT support
commit: 1cc1e851d15b4ebd4c6c5f741cfdb58b988a4445
[7/9] arm64: defconfig: Enable ROCKCHIP_LVDS
commit: dbb378a59cb2bdb01454098513d9b61355fbe377
[8/9] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY
commit: ec68a66395d9ccedc9b2b2f6452edfd7cb0fdfd5
[9/9] arm64: defconfig: Enable USB_SERIAL_CP210X
commit: cf35bff64f79b4ca8785766d67b608b76404d43f
Best regards,
--
Heiko Stuebner <[email protected]>