2020-11-11 16:32:36

by Sergio Paracuellos

Subject: [PATCH 2/7] dt: bindings: add mt7621-pll device tree binding documentation

Adds device tree binding documentation for PLL controller in
the MT7621 SOC.

Signed-off-by: Sergio Paracuellos <[email protected]>
---
.../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml
new file mode 100644
index 000000000000..ef58411065e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 PLL Controller Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <[email protected]>
+
+
+description: |
+ The PLL Controller provides the cpu clock as well as derived
+ clock for the bus and the peripherals.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: <include/dt-bindings/clock/mt7621-clk.h>.
+
+properties:
+ compatible:
+ const: mediatek,mt7621-pll
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+ clock-output-names:
+ maxItems: 3
+
+required:
+ - compatible
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7621-clk.h>
+
+ pll {
+ compatible = "mediatek,mt7621-pll";
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "ahb", "apb";
+ };
--
2.25.1

2020-11-16 21:23:36

by Rob Herring (Arm)

Subject: Re: [PATCH 2/7] dt: bindings: add mt7621-pll device tree binding documentation

On Wed, 11 Nov 2020 17:30:08 +0100, Sergio Paracuellos wrote:
> Adds device tree binding documentation for PLL controller in
> the MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos <[email protected]>
> ---
> .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml
>

Reviewed-by: Rob Herring <[email protected]>

2020-11-17 05:42:41

by Sergio Paracuellos

Subject: Re: [PATCH 2/7] dt: bindings: add mt7621-pll device tree binding documentation

Hi Rob,

On Mon, Nov 16, 2020 at 8:16 PM Rob Herring <[email protected]> wrote:
>
> On Wed, 11 Nov 2020 17:30:08 +0100, Sergio Paracuellos wrote:
> > Adds device tree binding documentation for PLL controller in
> > the MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos <[email protected]>
> > ---
> > .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml
> >
>
> Reviewed-by: Rob Herring <[email protected]>

Thanks for the review. In that series there were two clock bindings
relating the pll and gates, There were finally joined in only one
binding and driver. This is done in the v3 of this series sent on
friday. Thanks for your time in looking also into this new version,

Best regards,
Sergio Paracuellos