This patchset ports CPU clock detection for MT7621 from OpenWrt
and adds a complete clock plan for the mt7621 SOC.
The documentation for this SOC only talks about two registers
regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
all or some ip cores.
No documentation about a probably existent set of dividers for each ip
core is included in the datasheets. So we cannot make anything better,
AFAICT.
Looking into driver code, and some openWRT patched there are
another frequences which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.
We also have a buch of gate clocks with their parents:
- "hsdma": "150m"
- "fe": "250m"
- "sp_divtx": "270m"
- "timer": "50m"
- "pcm": "270m"
- "pio": "50m"
- "gdma": "bus"
- "nand": "125m"
- "i2c": "50m"
- "i2s": "270m"
- "spi": "bus"
- "uart1": "50m"
- "uart2": "50m"
- "uart3": "50m"
- "eth": "50m"
- "pcie0": "125m"
- "pcie1": "125m"
- "pcie2": "125m"
- "crypto": "250m"
- "shxc": "50m"
There was a previous attempt of doing this here[0] but the author
(Chuanhong Guo) did not wanted to make assumptions of a clock plan
for the platform that time. It seems that now he has a better idea of
how the clocks are dispossed for this SoC so he share code[1] where
some frequencies and clock parents for the gates are coded from a
real mediatek private clock plan.
I do really want this to be upstreamed so according to the comments
in previous attempt[0] from Oleksij Rempel and the frequencies in
code[1] I have tried to do this by myself.
All of this patches have been tested in a GNUBee PC1 resulting in a
working platform.
Changes in v3:
- Fix compilation warnings reported by kernel test robot because of
ignoring return values of 'of_clk_hw_register' in functions
'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
- Fix dts file and binding documentation 'clock-output-names'.
Changes in v2:
- Remove the following patches:
* dt: bindings: add mt7621-pll device tree binding documentation.
* MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
- Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
and binding 'mt7621-clk'.
- Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
because we need clocks available in 'plat_time_init' before setting up
the timer for the GIC.
- Use new fixed clocks as parents for different gates and deriving from 'xtal'
using frequencies in[1].
- Adapt dts file and bindings header and documentation for new changes.
- Change MAINTAINERS file to only contains clk-mt7621.c code and
mediatek,mt7621-clk.yaml file.
[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
Sergio Paracuellos (5):
dt-bindings: clock: add dt binding header for mt7621 clocks
dt: bindings: add mt7621-clk device tree binding documentation
clk: ralink: add clock driver for mt7621 SoC
staging: mt7621-dts: make use of new 'mt7621-clk'
MAINTAINERS: add MT7621 CLOCK maintainer
.../bindings/clock/mediatek,mt7621-clk.yaml | 61 +++
MAINTAINERS | 6 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ralink/Kconfig | 14 +
drivers/clk/ralink/Makefile | 2 +
drivers/clk/ralink/clk-mt7621.c | 408 ++++++++++++++++++
drivers/staging/mt7621-dts/gbpc1.dts | 11 -
drivers/staging/mt7621-dts/mt7621.dtsi | 72 ++--
include/dt-bindings/clock/mt7621-clk.h | 41 ++
10 files changed, 567 insertions(+), 50 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
create mode 100644 drivers/clk/ralink/Kconfig
create mode 100644 drivers/clk/ralink/Makefile
create mode 100644 drivers/clk/ralink/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
--
2.25.1
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1f088a29bc2..30822ad6837c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11142,6 +11142,12 @@ L: [email protected]
S: Maintained
F: drivers/net/wireless/mediatek/mt7601u/
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
MEDIATEK MT7621/28/88 I2C DRIVER
M: Stefan Roese <[email protected]>
L: [email protected]
--
2.25.1
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
drivers/staging/mt7621-dts/gbpc1.dts | 11 ----
drivers/staging/mt7621-dts/mt7621.dtsi | 72 ++++++++++++--------------
2 files changed, 33 insertions(+), 50 deletions(-)
diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@50000 {
};
};
-&sysclock {
- compatible = "fixed-clock";
- /* This is normally 1/4 of cpuclock */
- clock-frequency = <225000000>;
-};
-
-&cpuclock {
- compatible = "fixed-clock";
- clock-frequency = <900000000>;
-};
-
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 82aa93634eda..f64e66de4bf7 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/mt7621-clk.h>
/ {
#address-cells = <1>;
@@ -27,26 +28,13 @@ aliases {
serial0 = &uartlite;
};
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <880000000>;
- };
-
- sysclock: sysclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* This is normally 1/4 of cpuclock */
- clock-frequency = <220000000>;
- };
-
- mmc_clock: mmc_clock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
+ pll: pll {
+ compatible = "mediatek,mt7621-clk";
+ ralink,sysctl = <&sysc>;
+ #clock-cells = <1>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
};
mmc_fixed_3v3: fixedregulator@0 {
@@ -76,7 +64,7 @@ palmbus: palmbus@1E000000 {
#size-cells = <1>;
sysc: sysc@0 {
- compatible = "mtk,mt7621-sysc";
+ compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
@@ -100,8 +88,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&pll MT7621_CLK_I2C>;
+ clock-names = "i2c";
resets = <&rstctrl 16>;
reset-names = "i2c";
@@ -118,8 +106,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&pll MT7621_CLK_I2S>;
+ clock-names = "i2s";
resets = <&rstctrl 17>;
reset-names = "i2s";
@@ -155,8 +143,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysclock>;
- clock-frequency = <50000000>;
+ clocks = <&pll MT7621_CLK_UART1>;
+ clock-names = "uart1";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -172,7 +160,7 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&pll MT7621_CLK_SPI>;
resets = <&rstctrl 18>;
reset-names = "spi";
@@ -188,6 +176,8 @@ gdma: gdma@2800 {
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
+ clocks = <&pll MT7621_CLK_GDMA>;
+ clock-names = "gdma";
resets = <&rstctrl 14>;
reset-names = "dma";
@@ -205,6 +195,8 @@ hsdma: hsdma@7000 {
compatible = "mediatek,mt7621-hsdma";
reg = <0x7000 0x1000>;
+ clocks = <&pll MT7621_CLK_HSDMA>;
+ clock-names = "hsdma";
resets = <&rstctrl 5>;
reset-names = "hsdma";
@@ -315,11 +307,6 @@ rstctrl: rstctrl {
#reset-cells = <1>;
};
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
sdhci: sdhci@1E130000 {
status = "disabled";
@@ -338,7 +325,8 @@ sdhci: sdhci@1E130000 {
pinctrl-0 = <&sdhci_pins>;
pinctrl-1 = <&sdhci_pins>;
- clocks = <&mmc_clock &mmc_clock>;
+ clocks = <&pll MT7621_CLK_SHXC>,
+ <&pll MT7621_CLK_50M>;
clock-names = "source", "hclk";
interrupt-parent = <&gic>;
@@ -353,7 +341,7 @@ xhci: xhci@1E1C0000 {
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
- clocks = <&sysclock>;
+ clocks = <&pll MT7621_CLK_XTAL>;
clock-names = "sys_ck";
interrupt-parent = <&gic>;
@@ -372,7 +360,7 @@ gic: interrupt-controller@1fbc0000 {
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&cpuclock>;
+ clocks = <&pll MT7621_CLK_CPU>;
};
};
@@ -385,6 +373,9 @@ nand: nand@1e003000 {
0x1e003800 0x800>;
#address-cells = <1>;
#size-cells = <1>;
+
+ clocks = <&pll MT7621_CLK_NAND>;
+ clock-names = "nand";
};
ethsys: syscon@1e000000 {
@@ -398,8 +389,9 @@ ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysclock>;
- clock-names = "ethif";
+ clocks = <&pll MT7621_CLK_FE>,
+ <&pll MT7621_CLK_ETH>;
+ clock-names = "fe", "ethif";
#address-cells = <1>;
#size-cells = <0>;
@@ -532,7 +524,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
reset-names = "pcie0", "pcie1", "pcie2";
- clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+ clocks = <&pll MT7621_CLK_PCIE0>,
+ <&pll MT7621_CLK_PCIE1>,
+ <&pll MT7621_CLK_PCIE2>;
clock-names = "pcie0", "pcie1", "pcie2";
phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
phy-names = "pcie-phy0", "pcie-phy2";
--
2.25.1
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.
Looking into driver code, and some openWRT patched there are
another frequences which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.
We also have a buch of gate clocks with their parents:
* "hsdma": "150m"
* "fe": "250m"
* "sp_divtx": "270m"
* "timer": "50m"
* "pcm": "270m"
* "pio": "50m"
* "gdma": "bus"
* "nand": "125m"
* "i2c": "50m"
* "i2s": "270m"
* "spi": "bus"
* "uart1": "50m"
* "uart2": "50m"
* "uart3": "50m"
* "eth": "50m"
* "pcie0": "125m"
* "pcie1": "125m"
* "pcie2": "125m"
* "crypto": "250m"
* "shxc": "50m"
With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ralink/Kconfig | 14 ++
drivers/clk/ralink/Makefile | 2 +
drivers/clk/ralink/clk-mt7621.c | 408 ++++++++++++++++++++++++++++++++
5 files changed, 426 insertions(+)
create mode 100644 drivers/clk/ralink/Kconfig
create mode 100644 drivers/clk/ralink/Makefile
create mode 100644 drivers/clk/ralink/clk-mt7621.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c715d4681a0b..5f94c4329033 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf147eb1..6578e167b047 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
+obj-y += ralink/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index 000000000000..7e8697327e0c
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for mediatek mt7621 SoC"
+ depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+ bool "Clock driver for MediaTek MT7621"
+ depends on SOC_MT7621 || COMPILE_TEST
+ default SOC_MT7621
+ help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index 000000000000..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index 000000000000..733aecffd6a9
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos <[email protected]>
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <dt-bindings/clock/mt7621-clk.h>
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0 0x2c
+#define SYSC_REG_CLKCFG1 0x30
+#define SYSC_REG_CUR_CLK_STS 0x44
+
+#define MEMC_REG_CPU_PLL 0x648
+#define XTAL_MODE_SEL_MASK 0x7
+#define XTAL_MODE_SEL_SHIFT 6
+
+#define CPU_CLK_SEL_MASK 0x3
+#define CPU_CLK_SEL_SHIFT 30
+
+#define CUR_CPU_FDIV_MASK 0x1f
+#define CUR_CPU_FDIV_SHIFT 8
+#define CUR_CPU_FFRAC_MASK 0x1f
+#define CUR_CPU_FFRAC_SHIFT 0
+
+#define CPU_PLL_PREDIV_MASK 0x3
+#define CPU_PLL_PREDIV_SHIFT 12
+#define CPU_PLL_FBDIV_MASK 0x7f
+#define CPU_PLL_FBDIV_SHIFT 4
+
+#define MHZ(x) ((x) * 1000 * 1000)
+
+struct mt7621_clk_provider {
+ struct device_node *node;
+ struct regmap *syscon_regmap;
+ struct clk_hw_onecell_data *clk_data;
+};
+
+struct mt7621_clk {
+ struct mt7621_clk_provider *clk_prov;
+ struct clk_hw hw;
+};
+
+struct mt7621_fixed_clk {
+ u8 idx;
+ const char *name;
+ const char *parent_name;
+ struct mt7621_clk_provider *clk_prov;
+ unsigned long rate;
+ struct clk_hw *hw;
+};
+
+struct mt7621_gate {
+ u8 idx;
+ const char *name;
+ const char *parent_name;
+ struct mt7621_clk_provider *clk_prov;
+ u32 bit_idx;
+ struct clk_hw hw;
+};
+
+#define GATE(_id, _name, _pname, _shift) \
+ { \
+ .idx = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .clk_prov = NULL, \
+ .bit_idx = _shift \
+ }
+
+static struct mt7621_gate mt7621_gates[] = {
+ GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
+ GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
+ GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
+ GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
+ GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
+ GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
+ GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
+ GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
+ GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
+ GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
+ GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)),
+ GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
+ GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)),
+ GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)),
+ GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)),
+ GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)),
+ GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)),
+ GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)),
+ GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)),
+ GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30))
+};
+
+static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw)
+{
+ return container_of(hw, struct mt7621_gate, hw);
+}
+
+static int mt7621_gate_enable(struct clk_hw *hw)
+{
+ struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
+ struct regmap *scon = clk_gate->clk_prov->syscon_regmap;
+
+ return regmap_update_bits(scon, SYSC_REG_CLKCFG1,
+ clk_gate->bit_idx, clk_gate->bit_idx);
+}
+
+static void mt7621_gate_disable(struct clk_hw *hw)
+{
+ struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
+ struct regmap *scon = clk_gate->clk_prov->syscon_regmap;
+
+ regmap_update_bits(scon, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
+}
+
+static int mt7621_gate_is_enabled(struct clk_hw *hw)
+{
+ struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
+ struct regmap *scon = clk_gate->clk_prov->syscon_regmap;
+ unsigned int val;
+
+ if (regmap_read(scon, SYSC_REG_CLKCFG1, &val))
+ return 0;
+
+ return val & clk_gate->bit_idx;
+}
+
+static const struct clk_ops mt7621_gate_ops = {
+ .enable = mt7621_gate_enable,
+ .disable = mt7621_gate_disable,
+ .is_enabled = mt7621_gate_is_enabled,
+};
+
+static int mt7621_gate_ops_init(struct device_node *np,
+ struct mt7621_gate *sclk)
+{
+ struct clk_init_data init = {
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ .num_parents = 1,
+ .parent_names = &sclk->parent_name,
+ .ops = &mt7621_gate_ops,
+ .name = sclk->name,
+ };
+
+ sclk->hw.init = &init;
+ return of_clk_hw_register(np, &sclk->hw);
+}
+
+static int mt7621_register_gates(struct mt7621_clk_provider *clk_prov)
+{
+ struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data;
+ struct clk_hw **hws = (*clk_data)->hws;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
+ struct mt7621_gate *sclk = &mt7621_gates[i];
+
+ sclk->clk_prov = clk_prov;
+ ret = mt7621_gate_ops_init(clk_prov->node, sclk);
+ if (ret) {
+ pr_err("Couldn't register clock %s\n", sclk->name);
+ goto err_clk_unreg;
+ }
+
+ hws[sclk->idx] = &sclk->hw;
+ (*clk_data)->num++;
+ }
+
+ return 0;
+
+err_clk_unreg:
+ while (--i >= 0) {
+ struct mt7621_gate *sclk = &mt7621_gates[i];
+
+ clk_hw_unregister(&sclk->hw);
+ }
+ return ret;
+}
+
+#define FIXED(_id, _name, _pname, _rate) \
+ { \
+ .idx = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .clk_prov = NULL, \
+ .rate = _rate \
+ }
+
+static struct mt7621_fixed_clk mt7621_fixed_clks[] = {
+ FIXED(MT7621_CLK_50M, "50m", "xtal", MHZ(50)),
+ FIXED(MT7621_CLK_125M, "125m", "xtal", MHZ(125)),
+ FIXED(MT7621_CLK_150M, "150m", "xtal", MHZ(150)),
+ FIXED(MT7621_CLK_250M, "250m", "xtal", MHZ(250)),
+ FIXED(MT7621_CLK_270M, "270m", "xtal", MHZ(270)),
+};
+
+static int mt7621_register_fixed_clocks(struct mt7621_clk_provider *clk_prov)
+{
+ struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data;
+ struct clk_hw **hws = (*clk_data)->hws;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
+ struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i];
+
+ sclk->clk_prov = clk_prov;
+ sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
+ sclk->parent_name, 0,
+ sclk->rate);
+ if (IS_ERR(sclk->hw)) {
+ pr_err("Couldn't register clock %s\n", sclk->name);
+ ret = PTR_ERR(sclk->hw);
+ goto err_clk_unreg;
+ }
+
+ hws[sclk->idx] = sclk->hw;
+ (*clk_data)->num++;
+ }
+
+ return 0;
+
+err_clk_unreg:
+ while (--i >= 0) {
+ struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i];
+
+ clk_hw_unregister_fixed_rate(sclk->hw);
+ }
+ return ret;
+}
+
+static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct mt7621_clk, hw);
+}
+
+static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct mt7621_clk *clk = to_mt7621_clk(hw);
+ struct regmap *scon = clk->clk_prov->syscon_regmap;
+ u32 val;
+
+ regmap_read(scon, SYSC_REG_SYSTEM_CONFIG0, &val);
+ val = (val >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
+
+ if (val <= 2)
+ return MHZ(20);
+ else if (val <= 5)
+ return MHZ(40);
+
+ return MHZ(25);
+}
+
+static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
+ unsigned long xtal_clk)
+{
+ static const u32 prediv_tbl[] = { 0, 1, 2, 2 };
+ struct mt7621_clk *clk = to_mt7621_clk(hw);
+ struct regmap *scon = clk->clk_prov->syscon_regmap;
+ u32 clkcfg, clk_sel, curclk, ffiv, ffrac;
+ u32 pll, prediv, fbdiv;
+ unsigned long cpu_clk;
+
+ regmap_read(scon, SYSC_REG_CLKCFG0, &clkcfg);
+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
+
+ regmap_read(scon, SYSC_REG_CUR_CLK_STS, &curclk);
+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
+
+ switch (clk_sel) {
+ case 0:
+ cpu_clk = MHZ(500);
+ break;
+ case 1:
+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
+ break;
+ default:
+ cpu_clk = xtal_clk;
+ }
+
+ return cpu_clk / ffiv * ffrac;
+}
+
+static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate / 4;
+}
+
+#define CLK_BASE(_name, _parent, _recalc) { \
+ .init = &(struct clk_init_data) { \
+ .name = _name, \
+ .ops = &(const struct clk_ops) { \
+ .recalc_rate = _recalc, \
+ }, \
+ .parent_names = (const char *const[]) { _parent }, \
+ .num_parents = _parent ? 1 : 0 \
+ }, \
+}
+
+static struct mt7621_clk mt7621_clks_base[] = {
+ { NULL, CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
+ { NULL, CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
+ { NULL, CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
+};
+
+static int mt7621_register_top_clocks(struct mt7621_clk_provider *clk_prov)
+{
+ struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data;
+ struct clk_hw **hws = (*clk_data)->hws;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
+ struct mt7621_clk *sclk = &mt7621_clks_base[i];
+
+ sclk->clk_prov = clk_prov;
+ ret = of_clk_hw_register(clk_prov->node, &sclk->hw);
+ if (ret) {
+ pr_err("Couldn't register top clock %i\n", i);
+ goto err_clk_unreg;
+ }
+
+ hws[i] = &sclk->hw;
+ (*clk_data)->num++;
+ }
+
+ return 0;
+
+err_clk_unreg:
+ while (--i >= 0) {
+ struct mt7621_clk *sclk = &mt7621_clks_base[i];
+
+ clk_hw_unregister(&sclk->hw);
+ }
+ return ret;
+}
+
+static void __init mt7621_clk_init(struct device_node *node)
+{
+ struct mt7621_clk_provider *clk_prov;
+ struct clk_hw_onecell_data **clk_data;
+ int ret, count;
+
+ clk_prov = kzalloc(sizeof(*clk_prov), GFP_KERNEL);
+ if (!clk_prov)
+ return;
+
+ clk_prov->syscon_regmap = syscon_regmap_lookup_by_phandle(node, "ralink,sysctl");
+ if (IS_ERR(clk_prov->syscon_regmap)) {
+ pr_err("Could not get syscon regmap\n");
+ goto free_clk_prov;
+ }
+
+ clk_prov->node = node;
+
+ clk_data = &clk_prov->clk_data;
+ count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_gates);
+ *clk_data = kzalloc(struct_size(*clk_data, hws, count), GFP_KERNEL);
+ if (!*clk_data)
+ goto free_clk_prov;
+
+ ret = mt7621_register_top_clocks(clk_prov);
+ if (ret) {
+ pr_err("Couldn't register top clocks\n");
+ goto free_clk_data;
+ }
+
+ ret = mt7621_register_fixed_clocks(clk_prov);
+ if (ret) {
+ pr_err("Couldn't register fixed clocks\n");
+ goto free_clk_data;
+ }
+
+ ret = mt7621_register_gates(clk_prov);
+ if (ret) {
+ pr_err("Couldn't register fixed clock gates\n");
+ goto free_clk_data;
+ }
+
+ of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_prov->clk_data);
+
+ return;
+
+free_clk_data:
+ kfree(clk_prov->clk_data);
+
+free_clk_prov:
+ kfree(clk_prov);
+}
+
+CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-clk", mt7621_clk_init);
+
+MODULE_AUTHOR("Sergio Paracuellos <[email protected]>");
+MODULE_DESCRIPTION("Mediatek Mt7621 clock driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
Adds dt binding header for 'mediatek,mt7621-clk' clocks.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL 0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M 4
+#define MT7621_CLK_150M 5
+#define MT7621_CLK_250M 6
+#define MT7621_CLK_270M 7
+
+#define MT7621_CLK_HSDMA 8
+#define MT7621_CLK_FE 9
+#define MT7621_CLK_SP_DIVTX 10
+#define MT7621_CLK_TIMER 11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA 14
+#define MT7621_CLK_NAND 15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1 19
+#define MT7621_CLK_UART2 20
+#define MT7621_CLK_UART3 21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0 23
+#define MT7621_CLK_PCIE1 24
+#define MT7621_CLK_PCIE2 25
+#define MT7621_CLK_CRYPTO 26
+#define MT7621_CLK_SHXC 27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
--
2.25.1
Hi!
On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
<[email protected]> wrote:
> [...]
> diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> new file mode 100644
> index 000000000000..cf6f9216379d
> --- /dev/null
> +++ b/drivers/clk/ralink/Makefile
Why ralink? The clock design of mt7621 doesn't seem
to be part of ralink legacy stuff, and ralink is already
acquired by mediatek anyway.
I think it should be put in drivers/clk/mediatek instead.
--
Regards,
Chuanhong Guo
Hi,
On Thu, Nov 19, 2020 at 10:32 AM Chuanhong Guo <[email protected]> wrote:
>
> Hi!
>
> On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
> <[email protected]> wrote:
> > [...]
> > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > new file mode 100644
> > index 000000000000..cf6f9216379d
> > --- /dev/null
> > +++ b/drivers/clk/ralink/Makefile
>
> Why ralink? The clock design of mt7621 doesn't seem
> to be part of ralink legacy stuff, and ralink is already
> acquired by mediatek anyway.
> I think it should be put in drivers/clk/mediatek instead.
I don't really know. It seems in that directory only arm arch related
code from mediatek is included... but let's see what other people
think about this.
>
> --
> Regards,
> Chuanhong Guo
Best regards,
Sergio Paracuellos
On Fri, 13 Nov 2020 16:46:28 +0100, Sergio Paracuellos wrote:
> Adds dt binding header for 'mediatek,mt7621-clk' clocks.
>
> Signed-off-by: Sergio Paracuellos <[email protected]>
> ---
> include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
Acked-by: Rob Herring <[email protected]>