2020-12-08 07:24:42

by Shuosheng Huang

Subject: [PATCH v4 2/6] cpufreq: sun50i: add a100 cpufreq support

Add cpufreq nvmem based for allwinner a100 SoC, it's similar to h6.

Signed-off-by: Shuosheng Huang <[email protected]>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 32 ++++++++++++++++++++++++++
2 files changed, 33 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3776d960f405..2ebf5d9cb616 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = {
*/
static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "allwinner,sun50i-h6", },
+ { .compatible = "allwinner,sun50i-a100", },

{ .compatible = "calxeda,highbank", },
{ .compatible = "calxeda,ecx-2000", },
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 3c0531938d1a..aead98164373 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -22,6 +22,9 @@
#define SUN50I_H6_NVMEM_MASK 0x7
#define SUN50I_H6_NVMEM_SHIFT 5

+#define SUN50I_A100_NVMEM_MASK 0xf
+#define SUN50I_A100_NVMEM_SHIFT 12
+
struct sunxi_cpufreq_soc_data {
int (*efuse_xlate)(struct nvmem_cell *speedbin_nvmem);
};
@@ -52,6 +55,30 @@ static int sun50i_h6_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
return 0;
}

+static int sun50i_a100_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
+{
+ size_t len;
+ u32 *speedbin;
+ u32 efuse_value;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &
+ SUN50I_A100_NVMEM_MASK;
+ kfree(speedbin);
+
+ switch (efuse_value) {
+ case 0b100:
+ return 2;
+ case 0b010:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
/**
* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
* @soc_data: pointer to sunxi_cpufreq_soc_data context
@@ -184,8 +211,13 @@ static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
.efuse_xlate = sun50i_h6_efuse_xlate,
};

+static const struct sunxi_cpufreq_soc_data sun50i_a100_data = {
+ .efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
static const struct of_device_id sun50i_cpufreq_match_list[] = {
{ .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
+ { .compatible = "allwinner,sun50i-a100", .data = &sun50i_a100_data },
{}
};

--
2.28.0

2020-12-14 09:35:42

by Samuel Holland

Subject: Re: [PATCH v4 2/6] cpufreq: sun50i: add a100 cpufreq support

On 12/8/20 1:19 AM, Shuosheng Huang wrote:
> Add cpufreq nvmem based for allwinner a100 SoC, it's similar to h6.
>
> Signed-off-by: Shuosheng Huang <[email protected]>
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> drivers/cpufreq/sun50i-cpufreq-nvmem.c | 32 ++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 3776d960f405..2ebf5d9cb616 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = {
> */
> static const struct of_device_id blacklist[] __initconst = {
> { .compatible = "allwinner,sun50i-h6", },
> + { .compatible = "allwinner,sun50i-a100", },
>
> { .compatible = "calxeda,highbank", },
> { .compatible = "calxeda,ecx-2000", },
> diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> index 3c0531938d1a..aead98164373 100644
> --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> @@ -22,6 +22,9 @@
> #define SUN50I_H6_NVMEM_MASK 0x7
> #define SUN50I_H6_NVMEM_SHIFT 5
>
> +#define SUN50I_A100_NVMEM_MASK 0xf
> +#define SUN50I_A100_NVMEM_SHIFT 12
> +
> struct sunxi_cpufreq_soc_data {
> int (*efuse_xlate)(struct nvmem_cell *speedbin_nvmem);
> };
> @@ -52,6 +55,30 @@ static int sun50i_h6_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
> return 0;
> }
>
> +static int sun50i_a100_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
> +{
> + size_t len;
> + u32 *speedbin;
> + u32 efuse_value;
> +
> + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> + if (IS_ERR(speedbin))
> + return PTR_ERR(speedbin);
> +
> + efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &

This does not compile. `efuse` should be `speedbin`. And please remove
the cast after fixing the types of the variables to be `u16` instead of
`u32`.

Cheers,
Samuel

> + SUN50I_A100_NVMEM_MASK;
> + kfree(speedbin);
> +
> + switch (efuse_value) {
> + case 0b100:
> + return 2;
> + case 0b010:
> + return 1;
> + default:
> + return 0;
> + }
> +}
> +
> /**
> * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
> * @soc_data: pointer to sunxi_cpufreq_soc_data context
> @@ -184,8 +211,13 @@ static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
> .efuse_xlate = sun50i_h6_efuse_xlate,
> };
>
> +static const struct sunxi_cpufreq_soc_data sun50i_a100_data = {
> + .efuse_xlate = sun50i_a100_efuse_xlate,
> +};
> +
> static const struct of_device_id sun50i_cpufreq_match_list[] = {
> { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
> + { .compatible = "allwinner,sun50i-a100", .data = &sun50i_a100_data },
> {}
> };
>
>