From: Liam Beguin <[email protected]>
Hi,
The LMK04832 is an ultra-high performance clock conditioner with JEDEC
JESD204B support and is also pin compatible with the LMK0482x family of
devices.
This driver adds minimal support to configure the LMK04832 clocks using
the clock framework.
At the moment, this doesn't fully support JESD204B subclass 1.
I'm working on adding proper SYSREF support and will update this series
as soon as it's ready.
At this stage, I was hoping for some general feedback on the work done
so far and advice on a few points:
- Currently, nothing sets the VCO frequency. In a local version,
I used a devicetree property and clk_set_rate(lmk->vco.clk, vco_rate).
Should this be set using the parent_rate from inside the
lmk04832_sclk_round_rate() and lmk04832_dclk_round_rate() functions.
How would this affect VCO sub clocks?
- Should round_rate error out when the calculated rate is too far from
the desired rate? Other drivers don't seem to do that.
- Since this is device is compatible with the LMK0482x family, should
the driver be renamed to lmk048xx?
Thanks for your time,
Liam
Liam Beguin (1):
clk: add initial support for the lmk04832
.../devicetree/bindings/clock/ti,lmk04832.txt | 90 ++
drivers/clk/Kconfig | 7 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-lmk04832.c | 1357 +++++++++++++++++
4 files changed, 1455 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti,lmk04832.txt
create mode 100644 drivers/clk/clk-lmk04832.c
base-commit: 2c85ebc57b3e1817b6ce1a6b703928e113a90442
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2.27.0