AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't
have a clock generator (unlike J7200 base board). Here the clock from
the SERDES has to be routed to the PCIE connector. This series adds
support to drive reference clock output from SERDES and also adds
SERDES (torrent) and SERDES wrapper (WIZ) bindings.
Kishon Vijay Abraham I (7):
dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES
Wrapper
dt-bindings: phy: ti,phy-j721e-wiz: Add binding for phy_en_refclk
dt-bindings: phy: cadence-torrent: Add binding for refclk driver
dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
phy: ti: j721e-wiz: Configure full rate divider for AM64
phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>
phy: cadence-torrent: Add support to drive refclk out
.../bindings/phy/phy-cadence-torrent.yaml | 17 ++
.../bindings/phy/ti,phy-j721e-wiz.yaml | 23 ++-
drivers/phy/cadence/phy-cadence-torrent.c | 158 ++++++++++++++++++
drivers/phy/ti/phy-j721e-wiz.c | 158 +++++++++++++++++-
include/dt-bindings/mux/ti-serdes.h | 4 +
5 files changed, 354 insertions(+), 6 deletions(-)
--
2.17.1
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/cadence/phy-cadence-torrent.c | 158 ++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index f310e15d94cb..ad01fb61cfa4 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -8,6 +8,7 @@
#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
@@ -76,6 +77,8 @@
* register offsets from SD0801 PHY register block base (i.e MHDP
* register base + 0x500000)
*/
+#define CMN_CDIAG_REFCLK_OVRD 0x004CU
+#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
#define CMN_SSM_BANDGAP_TMR 0x0021U
#define CMN_SSM_BIAS_TMR 0x0022U
#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
@@ -206,6 +209,8 @@
#define RX_DIAG_ACYA 0x01FFU
/* PHY PCS common registers */
+#define PHY_PIPE_CMN_CTRL1 0x0000U
+#define PHY_ISO_CMN_CTRL 0x0008U
#define PHY_PLL_CFG 0x000EU
#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
@@ -231,6 +236,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
static const struct reg_field phy_reset_ctrl =
REG_FIELD(PHY_RESET, 8, 8);
+#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
+
+enum cdns_torrent_refclk_out_pcs {
+ PHY_ISO_CMN_CTRL_8,
+ PHY_PIPE_CMN_CTRL1_0,
+};
+
+#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
+
+enum cdns_torrent_refclk_out_cmn {
+ CMN_CDIAG_REFCLK_OVRD_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_1,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_5,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_6,
+};
+
+static const struct reg_field refclk_out_pcs_cfg[] = {
+ [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8, 8),
+ [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0),
+};
+
+static const struct reg_field refclk_out_cmn_cfg[] = {
+ [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
+};
+
enum cdns_torrent_phy_type {
TYPE_NONE,
TYPE_DP,
@@ -288,6 +323,16 @@ enum phy_powerstate {
POWERSTATE_A3 = 3,
};
+struct cdns_torrent_derived_refclk {
+ struct clk_hw hw;
+ struct regmap_field *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
+ struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
+ struct clk_init_data clk_data;
+};
+
+#define to_cdns_torrent_derived_refclk(_hw) \
+ container_of(_hw, struct cdns_torrent_derived_refclk, hw)
+
static int cdns_torrent_phy_init(struct phy *phy);
static int cdns_torrent_dp_init(struct phy *phy);
static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
@@ -1604,6 +1649,110 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
return ret;
}
+static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
+
+ return 0;
+}
+
+static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
+}
+
+static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+ int val;
+
+ regmap_field_read(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], &val);
+
+ return !!val;
+}
+
+static const struct clk_ops cdns_torrent_derived_refclk_ops = {
+ .enable = cdns_torrent_derived_refclk_enable,
+ .disable = cdns_torrent_derived_refclk_disable,
+ .is_enabled = cdns_torrent_derived_refclk_is_enabled,
+};
+
+static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy,
+ struct device_node *node)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk;
+ struct device *dev = cdns_phy->dev;
+ struct regmap_field *field;
+ struct clk_init_data *init;
+ unsigned int num_parents;
+ const char *parent_name;
+ struct regmap *regmap;
+ char clk_name[100];
+ struct clk *clk;
+ int ret, i;
+
+ derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
+ if (!derived_refclk)
+ return -ENOMEM;
+
+ num_parents = of_clk_get_parent_count(node);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
+ node->name);
+
+ init = &derived_refclk->clk_data;
+
+ init->ops = &cdns_torrent_derived_refclk_ops;
+ init->flags = 0;
+ init->parent_names = parent_name ? &parent_name : NULL;
+ init->num_parents = num_parents ? 1 : 0;
+ init->name = clk_name;
+
+ regmap = cdns_phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG; i++) {
+ field = devm_regmap_field_alloc(dev, regmap, refclk_out_pcs_cfg[i]);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PCS reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ derived_refclk->pcs_fields[i] = field;
+ }
+
+ regmap = cdns_phy->regmap_common_cdb;
+ for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG; i++) {
+ field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
+ if (IS_ERR(field)) {
+ dev_err(dev, "CMN reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ derived_refclk->cmn_fields[i] = field;
+ }
+
+ derived_refclk->hw.init = init;
+
+ clk = devm_clk_register(dev, &derived_refclk->hw);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ if (ret)
+ dev_err(dev, "Failed to add refrcv clock provider: %s\n",
+ clk_name);
+
+ return ret;
+}
+
static int cdns_torrent_phy_on(struct phy *phy)
{
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
@@ -2150,6 +2299,15 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
/* Enable APB */
reset_control_deassert(cdns_phy->apb_rst);
+ child = of_get_child_by_name(dev->of_node, "refclk-driver");
+ if (child) {
+ ret = cdns_torrent_derived_refclk_register(cdns_phy, child);
+ if (ret) {
+ dev_err(dev, "failed to register derived refclk\n");
+ return ret;
+ }
+ }
+
for_each_available_child_of_node(dev->of_node, child) {
struct phy *gphy;
--
2.17.1
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 43 +++++++++++++++++++++++++++++++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2a03191eac64..08acfab1ebe6 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -101,6 +101,13 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 24, 25),
};
+static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 22, 23),
+ REG_FIELD(WIZ_LANECTL(1), 22, 23),
+ REG_FIELD(WIZ_LANECTL(2), 22, 23),
+ REG_FIELD(WIZ_LANECTL(3), 22, 23),
+};
+
static const struct reg_field typec_ln10_swap =
REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
@@ -193,6 +200,7 @@ static struct wiz_clk_div_sel clk_div_sel[] = {
enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
+ AM64_WIZ_10G,
};
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
@@ -210,6 +218,7 @@ struct wiz {
struct regmap_field *p_align[WIZ_MAX_LANES];
struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
+ struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
@@ -380,7 +389,7 @@ static int wiz_regfield_init(struct wiz *wiz)
}
clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
clk_mux_sel->field =
devm_regmap_field_alloc(dev, regmap,
refclk_dig_sel_10g);
@@ -424,6 +433,14 @@ static int wiz_regfield_init(struct wiz *wiz)
i);
return PTR_ERR(wiz->p_standard_mode[i]);
}
+
+ wiz->p0_fullrt_div[i] =
+ devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
+ if (IS_ERR(wiz->p0_fullrt_div[i])) {
+ dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n",
+ i);
+ return PTR_ERR(wiz->p0_fullrt_div[i]);
+ }
}
wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
@@ -719,6 +736,19 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
return ret;
}
+static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
+{
+ int ret = 0;
+
+ if (wiz->type != AM64_WIZ_10G)
+ return 0;
+
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ ret = regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+
+ return ret;
+}
+
static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
@@ -742,6 +772,10 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
return ret;
}
+ ret = wiz_phy_fullrt_div(wiz, id - 1);
+ if (ret)
+ return ret;
+
if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
@@ -769,6 +803,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
},
+ {
+ .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
+ },
{}
};
MODULE_DEVICE_TABLE(of, wiz_id_table);
@@ -904,14 +941,14 @@ static int wiz_probe(struct platform_device *pdev)
wiz->dev = dev;
wiz->regmap = regmap;
wiz->num_lanes = num_lanes;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_mux_sel = clk_mux_sel_10g;
else
wiz->clk_mux_sel = clk_mux_sel_16g;
wiz->clk_div_sel = clk_div_sel;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
else
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
--
2.17.1
On 24-12-20, 17:12, Kishon Vijay Abraham I wrote:
> The frequency of the txmclk between PCIe and SERDES has
> changed to 250MHz from 500MHz. Configure full rate divider
> for AM64 accordingly.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> drivers/phy/ti/phy-j721e-wiz.c | 43 +++++++++++++++++++++++++++++++---
> 1 file changed, 40 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index 2a03191eac64..08acfab1ebe6 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -101,6 +101,13 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
> REG_FIELD(WIZ_LANECTL(3), 24, 25),
> };
>
> +static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
> + REG_FIELD(WIZ_LANECTL(0), 22, 23),
> + REG_FIELD(WIZ_LANECTL(1), 22, 23),
> + REG_FIELD(WIZ_LANECTL(2), 22, 23),
> + REG_FIELD(WIZ_LANECTL(3), 22, 23),
> +};
> +
> static const struct reg_field typec_ln10_swap =
> REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
>
> @@ -193,6 +200,7 @@ static struct wiz_clk_div_sel clk_div_sel[] = {
> enum wiz_type {
> J721E_WIZ_16G,
> J721E_WIZ_10G,
> + AM64_WIZ_10G,
> };
>
> #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
> @@ -210,6 +218,7 @@ struct wiz {
> struct regmap_field *p_align[WIZ_MAX_LANES];
> struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
> struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
> + struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
> struct regmap_field *pma_cmn_refclk_int_mode;
> struct regmap_field *pma_cmn_refclk_mode;
> struct regmap_field *pma_cmn_refclk_dig_div;
> @@ -380,7 +389,7 @@ static int wiz_regfield_init(struct wiz *wiz)
> }
>
> clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
> - if (wiz->type == J721E_WIZ_10G)
> + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
> clk_mux_sel->field =
> devm_regmap_field_alloc(dev, regmap,
> refclk_dig_sel_10g);
> @@ -424,6 +433,14 @@ static int wiz_regfield_init(struct wiz *wiz)
> i);
> return PTR_ERR(wiz->p_standard_mode[i]);
> }
> +
> + wiz->p0_fullrt_div[i] =
> + devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
> + if (IS_ERR(wiz->p0_fullrt_div[i])) {
> + dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n",
> + i);
single line?
> + return PTR_ERR(wiz->p0_fullrt_div[i]);
> + }
> }
>
> wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
> @@ -719,6 +736,19 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
> return ret;
> }
>
> +static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
> +{
> + int ret = 0;
drop the variable..
> +
> + if (wiz->type != AM64_WIZ_10G)
> + return 0;
> +
> + if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
> + ret = regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
return regmap_
> +
> + return ret;
return 0
> +}
> +
> static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> unsigned long id)
> {
> @@ -742,6 +772,10 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> return ret;
> }
>
> + ret = wiz_phy_fullrt_div(wiz, id - 1);
> + if (ret)
> + return ret;
> +
> if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
> ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
> else
> @@ -769,6 +803,9 @@ static const struct of_device_id wiz_id_table[] = {
> {
> .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
> },
> + {
> + .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, wiz_id_table);
> @@ -904,14 +941,14 @@ static int wiz_probe(struct platform_device *pdev)
> wiz->dev = dev;
> wiz->regmap = regmap;
> wiz->num_lanes = num_lanes;
> - if (wiz->type == J721E_WIZ_10G)
> + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
> wiz->clk_mux_sel = clk_mux_sel_10g;
> else
> wiz->clk_mux_sel = clk_mux_sel_16g;
>
> wiz->clk_div_sel = clk_div_sel;
>
> - if (wiz->type == J721E_WIZ_10G)
> + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
> wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
> else
> wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
> --
> 2.17.1
--
~Vinod