2020-12-30 03:42:43

by Jiaxun Yang

Subject: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.

Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Tiezhu Yang <[email protected]>
Tested-by: Tiezhu Yang <[email protected]>
---
arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..83548331ee94 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)

leaves += (c->icache.waysize) ? 2 : 1;

+ if (c->vcache.waysize) {
+ levels++;
+ leaves++;
+ }
+
if (c->scache.waysize) {
levels++;
leaves++;
@@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cpuinfo_mips *c = &current_cpu_data;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;

if (c->icache.waysize) {
- /* L1 caches are per core */
+ /* D/I caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
+ populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
+ level++;
} else {
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
+
+ if (c->vcache.waysize) {
+ /* Vcache is per core as well */
+ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}

if (c->scache.waysize) {
- /* L2 cache is per cluster */
+ /* Scache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
- populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
+ populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}

- if (c->tcache.waysize)
- populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
+ if (c->tcache.waysize) {
+ populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }

this_cpu_ci->cpu_map_populated = true;

--
2.30.0

2020-12-30 03:44:06

by Jiaxun Yang

Subject: [PATCH 2/2] MIPS: Loongson64: Set cluster for cores

cluster is required for cacheinfo to set shared_cpu_map correctly.

Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Tiezhu Yang <[email protected]>
Tested-by: Tiezhu Yang <[email protected]>
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e744e1bee49e..fae3a97d853c 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -403,6 +403,8 @@ static void __init loongson3_smp_setup(void)
__cpu_number_map[i] = num;
__cpu_logical_map[num] = i;
set_cpu_possible(num, true);
+ /* Loongson processors are always grouped by 4 */
+ cpu_set_cluster(&cpu_data[num], i / 4);
num++;
}
i++;
--
2.30.0

2020-12-31 00:27:44

by Huacai Chen

Subject: Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

Hi, Jiaxun,

On Wed, Dec 30, 2020 at 11:41 AM Jiaxun Yang <[email protected]> wrote:
>
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Reviewed-by: Tiezhu Yang <[email protected]>
> Tested-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
> index 47312c529410..83548331ee94 100644
> --- a/arch/mips/kernel/cacheinfo.c
> +++ b/arch/mips/kernel/cacheinfo.c
> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
>
> leaves += (c->icache.waysize) ? 2 : 1;
>
> + if (c->vcache.waysize) {
> + levels++;
> + leaves++;
> + }
> +
> if (c->scache.waysize) {
> levels++;
> leaves++;
> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
> struct cpuinfo_mips *c = &current_cpu_data;
> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> struct cacheinfo *this_leaf = this_cpu_ci->info_list;
> + int level = 1;
>
> if (c->icache.waysize) {
> - /* L1 caches are per core */
> + /* D/I caches are per core */
It seems "I/D caches" is better than "D/I caches", see
arch/mips/include/asm/cpu-info.h and search cache_desc.

Huacai
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
> + level++;
> } else {
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> + }
> +
> + if (c->vcache.waysize) {
> + /* Vcache is per core as well */
> + fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> + populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> }
>
> if (c->scache.waysize) {
> - /* L2 cache is per cluster */
> + /* Scache is per cluster */
> fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
> + populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> }
>
> - if (c->tcache.waysize)
> - populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
> + if (c->tcache.waysize) {
> + populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> + }
>
> this_cpu_ci->cpu_map_populated = true;
>
> --
> 2.30.0
>

2020-12-31 00:28:54

by Huacai Chen

Subject: Re: [PATCH 2/2] MIPS: Loongson64: Set cluster for cores

Reviewed-by: Huacai Chen <[email protected]>

On Wed, Dec 30, 2020 at 11:43 AM Jiaxun Yang <[email protected]> wrote:
>
> cluster is required for cacheinfo to set shared_cpu_map correctly.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Reviewed-by: Tiezhu Yang <[email protected]>
> Tested-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/loongson64/smp.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
> index e744e1bee49e..fae3a97d853c 100644
> --- a/arch/mips/loongson64/smp.c
> +++ b/arch/mips/loongson64/smp.c
> @@ -403,6 +403,8 @@ static void __init loongson3_smp_setup(void)
> __cpu_number_map[i] = num;
> __cpu_logical_map[num] = i;
> set_cpu_possible(num, true);
> + /* Loongson processors are always grouped by 4 */
> + cpu_set_cluster(&cpu_data[num], i / 4);
> num++;
> }
> i++;
> --
> 2.30.0
>

2021-01-04 10:50:41

by Thomas Bogendoerfer

Subject: Re: [PATCH 2/2] MIPS: Loongson64: Set cluster for cores

On Wed, Dec 30, 2020 at 11:39:49AM +0800, Jiaxun Yang wrote:
> cluster is required for cacheinfo to set shared_cpu_map correctly.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Reviewed-by: Tiezhu Yang <[email protected]>
> Tested-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/loongson64/smp.c | 2 ++
> 1 file changed, 2 insertions(+)

applied to mips-next.

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]

2021-01-04 10:51:27

by Thomas Bogendoerfer

Subject: Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

On Wed, Dec 30, 2020 at 11:39:48AM +0800, Jiaxun Yang wrote:
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Reviewed-by: Tiezhu Yang <[email protected]>
> Tested-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
> 1 file changed, 26 insertions(+), 8 deletions(-)

applied to mips-next.

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]