Patch series adds DT nodes in order to get PCIe working in J7200.
Also includes couple of fixes for J721e.
v1 of the patch series can be found @ [1]
v2 of the patch series can be found @ [2]
Changes from v2:
1) Moved serdes_refclk node out of interconnect node and also replaced
"_" with "-"
Changes from v1:
1) Include only the device tree patches here (the binding patch is sent
separately)
2) Include couple of patches that fixes J721E DTS.
[1] -> http://lore.kernel.org/r/[email protected]
[2] -> http://lore.kernel.org/r/[email protected]
Kishon Vijay Abraham I (6):
arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
pcieX_ctrl
arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
.../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
3 files changed, 157 insertions(+), 44 deletions(-)
--
2.17.1
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index def98f563336..4a7182abccf5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
@@ -241,3 +242,17 @@
resets = <&serdes_wiz0 3>;
};
};
+
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie1_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
--
2.17.1
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index fbe4cd1e6e09..4e39f0325c03 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -594,6 +594,54 @@
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = /bits/ 16 <0x104c>;
+ device-id = /bits/ 16 <0xb00f>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ dma-coherent;
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
Cadence IP in J721E supports a maximum of 32 outbound regions. However
commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device
tree nodes") incorrectly added this as 16 outbound regions. Now that
"cdns,max-outbound-regions" is an optional property with default value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index b32df591c766..1c11da612c67 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -651,7 +651,6 @@
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -700,7 +699,6 @@
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -749,7 +747,6 @@
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
@@ -798,7 +795,6 @@
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
--
2.17.1
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node
point to the parent with an offset argument. This change is as discussed in [1]
[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++-------------------
1 file changed, 8 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 1c11da612c67..2d526ea44a85 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -28,38 +28,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- pcie0_ctrl: syscon@4070 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004070 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4070 0x4070 0x4>;
- };
-
- pcie1_ctrl: syscon@4074 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004074 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4074 0x4074 0x4>;
- };
-
- pcie2_ctrl: syscon@4078 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00004078 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x4078 0x4078 0x4>;
- };
-
- pcie3_ctrl: syscon@407c {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x0000407c 0x4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x407c 0x407c 0x4>;
- };
-
serdes_ln_ctrl: mux@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
@@ -618,7 +586,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@@ -645,7 +613,7 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@@ -666,7 +634,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@@ -693,7 +661,7 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@@ -714,7 +682,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@@ -741,7 +709,7 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@@ -762,7 +730,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
@@ -789,7 +757,7 @@
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
--
2.17.1
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index b0094212aa82..fbe4cd1e6e09 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -5,6 +5,13 @@
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -531,6 +538,62 @@
dma-coherent;
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 292 85>;
+ assigned-clock-parents = <&k3_clks 292 89>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 85>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 85>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 331b388e1d1b..def98f563336 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -8,6 +8,7 @@
#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
/ {
chosen {
@@ -218,3 +219,25 @@
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 3>;
+ };
+};
--
2.17.1
On 17:52-20210104, Kishon Vijay Abraham I wrote:
> Cadence IP in J721E supports a maximum of 32 outbound regions. However
> commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device
> tree nodes") incorrectly added this as 16 outbound regions. Now that
> "cdns,max-outbound-regions" is an optional property with default value
> as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
>
> Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
^^ Is this a backward compatible fixup. If I were to apply this on
v5.10, wont we have a broken PCIe functionality? Drop the fixes if this
is not backward compatible fixup (unless ofcourse the driver fixup is
backported all the way back as well - I am assuming will be done in a
manner to preserve compatibility with older dtb?)
On master right now:
$ git grep "cdns,max-outbound-regions" .
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml: cdns,max-outbound-regions = <16>;
Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml: cdns,max-outbound-regions:
Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml: cdns,max-outbound-regions:
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi: cdns,max-outbound-regions = <16>;
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi: cdns,max-outbound-regions = <16>;
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi: cdns,max-outbound-regions = <16>;
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi: cdns,max-outbound-regions = <16>;
drivers/pci/controller/cadence/pcie-cadence-ep.c: of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions);
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ----
> 1 file changed, 4 deletions(-)
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
On 17:52-20210104, Kishon Vijay Abraham I wrote:
> Patch series adds DT nodes in order to get PCIe working in J7200.
> Also includes couple of fixes for J721e.
>
> v1 of the patch series can be found @ [1]
> v2 of the patch series can be found @ [2]
>
> Changes from v2:
> 1) Moved serdes_refclk node out of interconnect node and also replaced
> "_" with "-"
>
> Changes from v1:
> 1) Include only the device tree patches here (the binding patch is sent
> separately)
> 2) Include couple of patches that fixes J721E DTS.
>
> [1] -> http://lore.kernel.org/r/[email protected]
> [2] -> http://lore.kernel.org/r/[email protected]
>
> Kishon Vijay Abraham I (6):
> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
> pcieX_ctrl
> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
>
> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
> 3 files changed, 157 insertions(+), 44 deletions(-)
A bit confused on the dependency here. is there something merged into
next-20210104 that makes this series ready for pickup? is there a way
I can get a immutable tag for driver fixups to pull so that my dts
next is not broken for PCIe (I am assuming looking at the series that
this is probably not a backward compatible series?)?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Nishanth,
On 04/01/21 6:29 pm, Nishanth Menon wrote:
> On 17:52-20210104, Kishon Vijay Abraham I wrote:
>> Patch series adds DT nodes in order to get PCIe working in J7200.
>> Also includes couple of fixes for J721e.
>>
>> v1 of the patch series can be found @ [1]
>> v2 of the patch series can be found @ [2]
>>
>> Changes from v2:
>> 1) Moved serdes_refclk node out of interconnect node and also replaced
>> "_" with "-"
>>
>> Changes from v1:
>> 1) Include only the device tree patches here (the binding patch is sent
>> separately)
>> 2) Include couple of patches that fixes J721E DTS.
>>
>> [1] -> http://lore.kernel.org/r/[email protected]
>> [2] -> http://lore.kernel.org/r/[email protected]
>>
>> Kishon Vijay Abraham I (6):
>> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
>> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
>> pcieX_ctrl
>> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
>> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
>> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
>> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
>>
>> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
>> 3 files changed, 157 insertions(+), 44 deletions(-)
>
>
> A bit confused on the dependency here. is there something merged into
> next-20210104 that makes this series ready for pickup? is there a way
> I can get a immutable tag for driver fixups to pull so that my dts
> next is not broken for PCIe (I am assuming looking at the series that
> this is probably not a backward compatible series?)?
There are no driver changes for the basic J7200 PCIe support and the DT
bindings are already merged [1].
There are few errata fixes applicable for J721E which has to be removed
for J7200 but that depends on other patches to be merged [1] but that
doesn't impact j7200 functionality.
[1] ->
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
[2] -> http://lore.kernel.org/r/[email protected]
Thanks
Kishon
On 18:40-20210104, Kishon Vijay Abraham I wrote:
> Nishanth,
>
> On 04/01/21 6:29 pm, Nishanth Menon wrote:
> > On 17:52-20210104, Kishon Vijay Abraham I wrote:
> >> Patch series adds DT nodes in order to get PCIe working in J7200.
> >> Also includes couple of fixes for J721e.
> >>
> >> v1 of the patch series can be found @ [1]
> >> v2 of the patch series can be found @ [2]
> >>
> >> Changes from v2:
> >> 1) Moved serdes_refclk node out of interconnect node and also replaced
> >> "_" with "-"
> >>
> >> Changes from v1:
> >> 1) Include only the device tree patches here (the binding patch is sent
> >> separately)
> >> 2) Include couple of patches that fixes J721E DTS.
> >>
> >> [1] -> http://lore.kernel.org/r/[email protected]
> >> [2] -> http://lore.kernel.org/r/[email protected]
> >>
> >> Kishon Vijay Abraham I (6):
> >> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
> >> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
> >> pcieX_ctrl
> >> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
> >> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
> >> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
> >> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
> >>
> >> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
> >> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
> >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
> >> 3 files changed, 157 insertions(+), 44 deletions(-)
> >
> >
> > A bit confused on the dependency here. is there something merged into
> > next-20210104 that makes this series ready for pickup? is there a way
> > I can get a immutable tag for driver fixups to pull so that my dts
> > next is not broken for PCIe (I am assuming looking at the series that
> > this is probably not a backward compatible series?)?
>
> There are no driver changes for the basic J7200 PCIe support and the DT
> bindings are already merged [1].
>
> There are few errata fixes applicable for J721E which has to be removed
> for J7200 but that depends on other patches to be merged [1] but that
> doesn't impact j7200 functionality.
>
> [1] ->
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
> [2] -> http://lore.kernel.org/r/[email protected]
So, Dropping stuff like "cdns,max-outbound-regions" (change from 16 to
32) will work on older kernels? Could you do a quick sanity check on the
couple of "fixes" patches in this thread is not breaking functionality
introduced in the older stable kernels?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Nishanth,
On 04/01/21 6:46 pm, Nishanth Menon wrote:
> On 18:40-20210104, Kishon Vijay Abraham I wrote:
>> Nishanth,
>>
>> On 04/01/21 6:29 pm, Nishanth Menon wrote:
>>> On 17:52-20210104, Kishon Vijay Abraham I wrote:
>>>> Patch series adds DT nodes in order to get PCIe working in J7200.
>>>> Also includes couple of fixes for J721e.
>>>>
>>>> v1 of the patch series can be found @ [1]
>>>> v2 of the patch series can be found @ [2]
>>>>
>>>> Changes from v2:
>>>> 1) Moved serdes_refclk node out of interconnect node and also replaced
>>>> "_" with "-"
>>>>
>>>> Changes from v1:
>>>> 1) Include only the device tree patches here (the binding patch is sent
>>>> separately)
>>>> 2) Include couple of patches that fixes J721E DTS.
>>>>
>>>> [1] -> http://lore.kernel.org/r/[email protected]
>>>> [2] -> http://lore.kernel.org/r/[email protected]
>>>>
>>>> Kishon Vijay Abraham I (6):
>>>> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
>>>> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
>>>> pcieX_ctrl
>>>> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
>>>> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
>>>>
>>>> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
>>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
>>>> 3 files changed, 157 insertions(+), 44 deletions(-)
>>>
>>>
>>> A bit confused on the dependency here. is there something merged into
>>> next-20210104 that makes this series ready for pickup? is there a way
>>> I can get a immutable tag for driver fixups to pull so that my dts
>>> next is not broken for PCIe (I am assuming looking at the series that
>>> this is probably not a backward compatible series?)?
>>
>> There are no driver changes for the basic J7200 PCIe support and the DT
>> bindings are already merged [1].
>>
>> There are few errata fixes applicable for J721E which has to be removed
>> for J7200 but that depends on other patches to be merged [1] but that
>> doesn't impact j7200 functionality.
>>
>> [1] ->
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
>> [2] -> http://lore.kernel.org/r/[email protected]
>
> So, Dropping stuff like "cdns,max-outbound-regions" (change from 16 to
> 32) will work on older kernels? Could you do a quick sanity check on the
> couple of "fixes" patches in this thread is not breaking functionality
> introduced in the older stable kernels?
Okay, the driver changes are done such that it works with both old DT
and new DT however the newer DT will not work with old kernel. So I
think I should drop the "Fixes" tag in the DT patches.
Thanks
Kishon
On 18:52-20210104, Kishon Vijay Abraham I wrote:
> Nishanth,
>
> On 04/01/21 6:46 pm, Nishanth Menon wrote:
> > On 18:40-20210104, Kishon Vijay Abraham I wrote:
> >> Nishanth,
> >>
> >> On 04/01/21 6:29 pm, Nishanth Menon wrote:
> >>> On 17:52-20210104, Kishon Vijay Abraham I wrote:
> >>>> Patch series adds DT nodes in order to get PCIe working in J7200.
> >>>> Also includes couple of fixes for J721e.
> >>>>
> >>>> v1 of the patch series can be found @ [1]
> >>>> v2 of the patch series can be found @ [2]
> >>>>
> >>>> Changes from v2:
> >>>> 1) Moved serdes_refclk node out of interconnect node and also replaced
> >>>> "_" with "-"
> >>>>
> >>>> Changes from v1:
> >>>> 1) Include only the device tree patches here (the binding patch is sent
> >>>> separately)
> >>>> 2) Include couple of patches that fixes J721E DTS.
> >>>>
> >>>> [1] -> http://lore.kernel.org/r/[email protected]
> >>>> [2] -> http://lore.kernel.org/r/[email protected]
> >>>>
> >>>> Kishon Vijay Abraham I (6):
> >>>> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
> >>>> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
> >>>> pcieX_ctrl
> >>>> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
> >>>> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
> >>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
> >>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
> >>>>
> >>>> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
> >>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
> >>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
> >>>> 3 files changed, 157 insertions(+), 44 deletions(-)
> >>>
> >>>
> >>> A bit confused on the dependency here. is there something merged into
> >>> next-20210104 that makes this series ready for pickup? is there a way
> >>> I can get a immutable tag for driver fixups to pull so that my dts
> >>> next is not broken for PCIe (I am assuming looking at the series that
> >>> this is probably not a backward compatible series?)?
> >>
> >> There are no driver changes for the basic J7200 PCIe support and the DT
> >> bindings are already merged [1].
> >>
> >> There are few errata fixes applicable for J721E which has to be removed
> >> for J7200 but that depends on other patches to be merged [1] but that
> >> doesn't impact j7200 functionality.
> >>
> >> [1] ->
> >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
> >> [2] -> http://lore.kernel.org/r/[email protected]
> >
> > So, Dropping stuff like "cdns,max-outbound-regions" (change from 16 to
> > 32) will work on older kernels? Could you do a quick sanity check on the
> > couple of "fixes" patches in this thread is not breaking functionality
> > introduced in the older stable kernels?
>
> Okay, the driver changes are done such that it works with both old DT
> and new DT however the newer DT will not work with old kernel. So I
> think I should drop the "Fixes" tag in the DT patches.
If there is a specific stable kernel version you might like to use, you
could use that as well for those stable tags (see [1])
[1] https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Nishanth,
On 04/01/21 8:21 pm, Nishanth Menon wrote:
> On 18:52-20210104, Kishon Vijay Abraham I wrote:
>> Nishanth,
>>
>> On 04/01/21 6:46 pm, Nishanth Menon wrote:
>>> On 18:40-20210104, Kishon Vijay Abraham I wrote:
>>>> Nishanth,
>>>>
>>>> On 04/01/21 6:29 pm, Nishanth Menon wrote:
>>>>> On 17:52-20210104, Kishon Vijay Abraham I wrote:
>>>>>> Patch series adds DT nodes in order to get PCIe working in J7200.
>>>>>> Also includes couple of fixes for J721e.
>>>>>>
>>>>>> v1 of the patch series can be found @ [1]
>>>>>> v2 of the patch series can be found @ [2]
>>>>>>
>>>>>> Changes from v2:
>>>>>> 1) Moved serdes_refclk node out of interconnect node and also replaced
>>>>>> "_" with "-"
>>>>>>
>>>>>> Changes from v1:
>>>>>> 1) Include only the device tree patches here (the binding patch is sent
>>>>>> separately)
>>>>>> 2) Include couple of patches that fixes J721E DTS.
>>>>>>
>>>>>> [1] -> http://lore.kernel.org/r/[email protected]
>>>>>> [2] -> http://lore.kernel.org/r/[email protected]
>>>>>>
>>>>>> Kishon Vijay Abraham I (6):
>>>>>> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
>>>>>> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
>>>>>> pcieX_ctrl
>>>>>> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
>>>>>> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
>>>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
>>>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
>>>>>>
>>>>>> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
>>>>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
>>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
>>>>>> 3 files changed, 157 insertions(+), 44 deletions(-)
>>>>>
>>>>>
>>>>> A bit confused on the dependency here. is there something merged into
>>>>> next-20210104 that makes this series ready for pickup? is there a way
>>>>> I can get a immutable tag for driver fixups to pull so that my dts
>>>>> next is not broken for PCIe (I am assuming looking at the series that
>>>>> this is probably not a backward compatible series?)?
>>>>
>>>> There are no driver changes for the basic J7200 PCIe support and the DT
>>>> bindings are already merged [1].
>>>>
>>>> There are few errata fixes applicable for J721E which has to be removed
>>>> for J7200 but that depends on other patches to be merged [1] but that
>>>> doesn't impact j7200 functionality.
>>>>
>>>> [1] ->
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
>>>> [2] -> http://lore.kernel.org/r/[email protected]
>>>
>>> So, Dropping stuff like "cdns,max-outbound-regions" (change from 16 to
>>> 32) will work on older kernels? Could you do a quick sanity check on the
>>> couple of "fixes" patches in this thread is not breaking functionality
>>> introduced in the older stable kernels?
>>
>> Okay, the driver changes are done such that it works with both old DT
>> and new DT however the newer DT will not work with old kernel. So I
>> think I should drop the "Fixes" tag in the DT patches.
>
> If there is a specific stable kernel version you might like to use, you
> could use that as well for those stable tags (see [1])
It's not a fix that might bother people (as it doesn't impact existing
functionality), so don't think it's a candidate for stable releases.
Thanks
Kishon
>
>
> [1] https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
>
On 21:01-20210104, Kishon Vijay Abraham I wrote:
> Nishanth,
>
> On 04/01/21 8:21 pm, Nishanth Menon wrote:
> > On 18:52-20210104, Kishon Vijay Abraham I wrote:
> >> Nishanth,
> >>
> >> On 04/01/21 6:46 pm, Nishanth Menon wrote:
> >>> On 18:40-20210104, Kishon Vijay Abraham I wrote:
> >>>> Nishanth,
> >>>>
> >>>> On 04/01/21 6:29 pm, Nishanth Menon wrote:
> >>>>> On 17:52-20210104, Kishon Vijay Abraham I wrote:
> >>>>>> Patch series adds DT nodes in order to get PCIe working in J7200.
> >>>>>> Also includes couple of fixes for J721e.
> >>>>>>
> >>>>>> v1 of the patch series can be found @ [1]
> >>>>>> v2 of the patch series can be found @ [2]
> >>>>>>
> >>>>>> Changes from v2:
> >>>>>> 1) Moved serdes_refclk node out of interconnect node and also replaced
> >>>>>> "_" with "-"
> >>>>>>
> >>>>>> Changes from v1:
> >>>>>> 1) Include only the device tree patches here (the binding patch is sent
> >>>>>> separately)
> >>>>>> 2) Include couple of patches that fixes J721E DTS.
> >>>>>>
> >>>>>> [1] -> http://lore.kernel.org/r/[email protected]
> >>>>>> [2] -> http://lore.kernel.org/r/[email protected]
> >>>>>>
> >>>>>> Kishon Vijay Abraham I (6):
> >>>>>> arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
> >>>>>> arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
> >>>>>> pcieX_ctrl
> >>>>>> arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
> >>>>>> arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
> >>>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
> >>>>>> arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
> >>>>>>
> >>>>>> .../dts/ti/k3-j7200-common-proc-board.dts | 38 ++++++
> >>>>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 111 ++++++++++++++++++
> >>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 52 ++------
> >>>>>> 3 files changed, 157 insertions(+), 44 deletions(-)
> >>>>>
> >>>>>
> >>>>> A bit confused on the dependency here. is there something merged into
> >>>>> next-20210104 that makes this series ready for pickup? is there a way
> >>>>> I can get a immutable tag for driver fixups to pull so that my dts
> >>>>> next is not broken for PCIe (I am assuming looking at the series that
> >>>>> this is probably not a backward compatible series?)?
> >>>>
> >>>> There are no driver changes for the basic J7200 PCIe support and the DT
> >>>> bindings are already merged [1].
> >>>>
> >>>> There are few errata fixes applicable for J721E which has to be removed
> >>>> for J7200 but that depends on other patches to be merged [1] but that
> >>>> doesn't impact j7200 functionality.
> >>>>
> >>>> [1] ->
> >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml#n19
> >>>> [2] -> http://lore.kernel.org/r/[email protected]
> >>>
> >>> So, Dropping stuff like "cdns,max-outbound-regions" (change from 16 to
> >>> 32) will work on older kernels? Could you do a quick sanity check on the
> >>> couple of "fixes" patches in this thread is not breaking functionality
> >>> introduced in the older stable kernels?
> >>
> >> Okay, the driver changes are done such that it works with both old DT
> >> and new DT however the newer DT will not work with old kernel. So I
> >> think I should drop the "Fixes" tag in the DT patches.
> >
> > If there is a specific stable kernel version you might like to use, you
> > could use that as well for those stable tags (see [1])
>
> It's not a fix that might bother people (as it doesn't impact existing
> functionality), so don't think it's a candidate for stable releases.
OK. please repost without the fixes tag.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D