2021-01-08 14:01:49

by Peter Geis

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Subject: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver

Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Acked-by: Jon Hunter <[email protected]>
Tested-by: Ion Agorria <[email protected]>
Signed-off-by: Peter Geis <[email protected]>
---
drivers/clk/tegra/clk-tegra30.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 37244a7e68c2..9cf249c344d9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
+ { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
+ { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
/* must be the last entry */
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
};
--
2.25.1


2021-01-08 15:16:31

by Sameer Pujar

[permalink] [raw]
Subject: Re: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver



On 1/8/2021 7:29 PM, Peter Geis wrote:
> External email: Use caution opening links or attachments
>
>
> Current implementation defaults the hda clocks to clk_m. This causes hda
> to run too slow to operate correctly. Fix this by defaulting to pll_p and
> setting the frequency to the correct rate.
>
> This matches upstream t124 and downstream t30.
>
> Acked-by: Jon Hunter <[email protected]>
> Tested-by: Ion Agorria <[email protected]>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> drivers/clk/tegra/clk-tegra30.c | 2 ++
> 1 file changed, 2 insertions(+)

Acked-by: Sameer Pujar <[email protected]>

2021-01-12 13:09:56

by Thierry Reding

[permalink] [raw]
Subject: Re: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock driver

On Fri, Jan 08, 2021 at 01:59:12PM +0000, Peter Geis wrote:
> Current implementation defaults the hda clocks to clk_m. This causes hda
> to run too slow to operate correctly. Fix this by defaulting to pll_p and
> setting the frequency to the correct rate.
>
> This matches upstream t124 and downstream t30.
>
> Acked-by: Jon Hunter <[email protected]>
> Tested-by: Ion Agorria <[email protected]>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> drivers/clk/tegra/clk-tegra30.c | 2 ++
> 1 file changed, 2 insertions(+)

Acked-by: Thierry Reding <[email protected]>


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