The ACGR register is at the offset of 0x1024, beyond the 4k originally
assigned to the MPMU range.
Signed-off-by: Lubomir Rintel <[email protected]>
---
arch/arm/boot/dts/mmp3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
index 4ae630d37d094..9f2b059f0900b 100644
--- a/arch/arm/boot/dts/mmp3.dtsi
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -567,7 +567,7 @@ l2: cache-controller@d0020000 {
soc_clocks: clocks@d4050000 {
compatible = "marvell,mmp3-clock";
- reg = <0xd4050000 0x1000>,
+ reg = <0xd4050000 0x2000>,
<0xd4282800 0x400>,
<0xd4015000 0x1000>;
reg-names = "mpmu", "apmu", "apbc";
--
2.29.2