From: Konstantin Porotchkin <[email protected]>
This series of patches adds a new PHY driver for supporting CP110 UTMI
PHY in Linux. Currently the functionality of USB ports connected to
this PHY depends on boot loader setup.
The new driver eliminates kernel configuration dependency from the boot
loader.
Konstantin Porotchkin (4):
drivers: phy: add support for Armada CP110 UTMI PHY
devicetree/bindings: add support for CP110 UTMI driver
arch/arm64: dts: add support for Marvell CP110 UTMI driver
arch/arm64: dts: enable CP110 UTMI driver
.../bindings/phy/phy-mvebu-utmi.txt | 69 +++-
.../arm64/boot/dts/marvell/armada-7040-db.dts | 12 +-
.../arm64/boot/dts/marvell/armada-8040-db.dts | 18 +-
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 16 +-
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +
arch/arm64/boot/dts/marvell/cn9130-db.dts | 10 +-
arch/arm64/boot/dts/marvell/cn9131-db.dts | 8 +-
arch/arm64/boot/dts/marvell/cn9132-db.dts | 9 +-
drivers/phy/marvell/Kconfig | 8 +
drivers/phy/marvell/Makefile | 1 +
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 372 ++++++++++++++++++
11 files changed, 522 insertions(+), 20 deletions(-)
create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Enable support for CP110 UTMI driver in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 12 ++++++++----
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 ++++++++++++++++--
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 16 ++++++++++++++--
arch/arm64/boot/dts/marvell/cn9130-db.dts | 10 ++++++++--
arch/arm64/boot/dts/marvell/cn9131-db.dts | 8 ++++++--
arch/arm64/boot/dts/marvell/cn9132-db.dts | 9 +++++++--
6 files changed, 59 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..ef792b932912 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -218,6 +218,10 @@
};
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_comphy1 {
cp0_usbh0_con: connector {
compatible = "usb-a-connector";
@@ -226,8 +230,8 @@
};
&cp0_usb3_0 {
- phys = <&cp0_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
+ phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
status = "okay";
};
@@ -239,8 +243,8 @@
};
&cp0_usb3_1 {
- phys = <&cp0_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "cp0-usb3h1-comphy", "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..f1af6beeb9f9 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -154,8 +154,14 @@
};
/* CON9 on CP0 expansion */
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
@@ -168,8 +174,8 @@
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
- phys = <&cp0_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "usb", "utmi";
status = "okay";
};
@@ -306,14 +312,22 @@
};
};
+&cp1_utmi {
+ status = "okay";
+};
+
/* CON9 on CP1 expansion */
&cp1_usb3_0 {
usb-phy = <&cp1_usb3_0_phy>;
+ phys = <&cp1_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
/* CON10 on CP1 expansion */
&cp1_usb3_1 {
+ phys = <&cp1_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..b3258a3984a3 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -259,13 +259,21 @@
vqmmc-supply = <&v_3_3>;
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
/* J38? - USB2.0 only */
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
&cp0_usb3_1 {
/* J38? - USB2.0 only */
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
@@ -364,9 +372,13 @@
};
};
+&cp1_utmi {
+ status = "okay";
+};
+
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
- phys = <&cp1_comphy2 0>;
- phy-names = "cp1-usb3h0-comphy";
+ phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
+ phy-names = "cp1-usb3h0-comphy", "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..02218422509c 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -390,14 +390,20 @@
};
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy0>;
- phy-names = "usb";
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
};
&cp0_usb3_1 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy1>;
- phy-names = "usb";
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..17e189875182 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -193,10 +193,14 @@
};
/* CON58 */
+&cp1_utmi {
+ status = "okay";
+};
+
&cp1_usb3_1 {
status = "okay";
usb-phy = <&cp1_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy3 1>;
- phy-names = "usb";
+ phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
+ phy-names = "usb", "utmi";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts
index 4ef0df3097ca..87da1dc3707c 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dts
@@ -205,9 +205,14 @@
};
};
+&cp2_utmi {
+ status = "okay";
+};
+
&cp2_usb3_0 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy0>;
+ phys = <&cp2_utmi0>;
phy-names = "usb";
};
@@ -215,7 +220,7 @@
&cp2_usb3_1 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy1>;
- phy-names = "usb";
/* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy3 1>;
+ phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
+ phy-names = "usb", "utmi";
};
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add support for Marvell CP110 UTMI PHY driver allowing the USB2
port configuration independently from the boot loader setup.
The CP110/CP115 dies have 2 UTMI PHYs that could be connected
to two USB host controllers or to single USB device controller.
Since there is only one USB device controller on die, only one
of the UTMI PHYs could work in USB device mode.
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
drivers/phy/marvell/Kconfig | 8 +
drivers/phy/marvell/Makefile | 1 +
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 372 ++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
index 6c96f2bf5266..9208839019bd 100644
--- a/drivers/phy/marvell/Kconfig
+++ b/drivers/phy/marvell/Kconfig
@@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY
lanes can be used by various controllers (Ethernet, sata, usb,
PCIe...).
+config PHY_MVEBU_CP110_UTMI
+ tristate "Marvell CP110 UTMI driver"
+ depends on ARCH_MVEBU || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support Marvell CP110 UTMI PHY driver.
+
config PHY_MVEBU_SATA
def_bool y
depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD
diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
index 7f296ef02829..90862c4daa26 100644
--- a/drivers/phy/marvell/Makefile
+++ b/drivers/phy/marvell/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o
obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
+obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
new file mode 100644
index 000000000000..3a7499b24671
--- /dev/null
+++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Marvell
+ *
+ * Authors:
+ * Konstantin Porotchkin <[email protected]>
+ *
+ * Marvell CP110 UTMI PHY driver
+ */
+
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define UTMI_PHY_PORTS 2
+
+/* CP110 UTMI register macro definetions */
+#define SYSCON_USB_CFG_REG 0x420
+#define USB_CFG_DEVICE_EN_MASK BIT(0)
+#define USB_CFG_DEVICE_MUX_OFFSET 1
+#define USB_CFG_DEVICE_MUX_MASK BIT(1)
+#define USB_CFG_PLL_MASK BIT(25)
+
+#define SYSCON_UTMI_CFG_REG(id) (0x440 + (id) * 4)
+#define UTMI_PHY_CFG_PU_MASK BIT(5)
+
+#define UTMI_PLL_CTRL_REG 0x0
+#define PLL_REFDIV_OFFSET 0
+#define PLL_REFDIV_MASK GENMASK(6, 0)
+#define PLL_REFDIV_VAL 0x5
+#define PLL_FBDIV_OFFSET 16
+#define PLL_FBDIV_MASK GENMASK(24, 16)
+#define PLL_FBDIV_VAL 0x60
+#define PLL_SEL_LPFR_MASK GENMASK(29, 28)
+#define PLL_RDY BIT(31)
+#define UTMI_CAL_CTRL_REG 0x8
+#define IMPCAL_VTH_OFFSET 8
+#define IMPCAL_VTH_MASK GENMASK(10, 8)
+#define IMPCAL_VTH_VAL 0x7
+#define IMPCAL_DONE BIT(23)
+#define PLLCAL_DONE BIT(31)
+#define UTMI_TX_CH_CTRL_REG 0xC
+#define DRV_EN_LS_OFFSET 12
+#define DRV_EN_LS_MASK GENMASK(15, 12)
+#define IMP_SEL_LS_OFFSET 16
+#define IMP_SEL_LS_MASK GENMASK(19, 16)
+#define TX_AMP_OFFSET 20
+#define TX_AMP_MASK GENMASK(22, 20)
+#define TX_AMP_VAL 0x4
+#define UTMI_RX_CH_CTRL0_REG 0x14
+#define SQ_DET_EN BIT(15)
+#define SQ_ANA_DTC_SEL BIT(28)
+#define UTMI_RX_CH_CTRL1_REG 0x18
+#define SQ_AMP_CAL_OFFSET 0
+#define SQ_AMP_CAL_MASK GENMASK(2, 0)
+#define SQ_AMP_CAL_VAL 1
+#define SQ_AMP_CAL_EN BIT(3)
+#define UTMI_CTRL_STATUS0_REG 0x24
+#define SUSPENDM BIT(22)
+#define TEST_SEL BIT(25)
+#define UTMI_CHGDTC_CTRL_REG 0x38
+#define VDAT_OFFSET 8
+#define VDAT_MASK GENMASK(9, 8)
+#define VDAT_VAL 1
+#define VSRC_OFFSET 10
+#define VSRC_MASK GENMASK(11, 10)
+#define VSRC_VAL 1
+
+#define PLL_LOCK_DELAY_US 10000
+#define PLL_LOCK_TIMEOUT_US 1000000
+
+#define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000)
+
+/**
+ * struct mvebu_cp110_utmi - PHY driver data
+ *
+ * @regs: PHY registers
+ * @syscom: Regmap with system controller registers
+ * @dev: device driver handle
+ * @caps: PHY capabilities
+ */
+struct mvebu_cp110_utmi {
+ void __iomem *regs;
+ struct regmap *syscon;
+ struct device *dev;
+ const struct phy_ops *ops;
+};
+
+/**
+ * struct mvebu_cp110_utmi_port - PHY port data
+ *
+ * @priv: PHY driver data
+ * @id: PHY port ID
+ * @device_mode: PHY connection - 1 for USB device, 0 for USB host
+ */
+struct mvebu_cp110_utmi_port {
+ struct mvebu_cp110_utmi *priv;
+ u32 id;
+ bool device_mode;
+};
+
+static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port *port)
+{
+ u32 reg;
+
+ /*
+ * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
+ * See the functional specification for details.
+ */
+ reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG);
+ reg &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK | PLL_SEL_LPFR_MASK);
+ reg |= (PLL_REFDIV_VAL << PLL_REFDIV_OFFSET) |
+ (PLL_FBDIV_VAL << PLL_FBDIV_OFFSET);
+ writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG);
+
+ /* Impedance Calibration Threshold Setting */
+ reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG);
+ reg &= ~IMPCAL_VTH_MASK;
+ reg |= IMPCAL_VTH_VAL << IMPCAL_VTH_OFFSET;
+ writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG);
+
+ /* Set LS TX driver strength coarse control */
+ reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
+ reg &= ~TX_AMP_MASK;
+ reg |= TX_AMP_VAL << TX_AMP_OFFSET;
+ writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
+
+ /* Disable SQ and enable analog squelch detect */
+ reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
+ reg &= ~SQ_DET_EN;
+ reg |= SQ_ANA_DTC_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
+
+ /*
+ * Set External squelch calibration number and
+ * enable the External squelch calibration
+ */
+ reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
+ reg &= ~SQ_AMP_CAL_MASK;
+ reg |= (SQ_AMP_CAL_VAL << SQ_AMP_CAL_OFFSET) | SQ_AMP_CAL_EN;
+ writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
+
+ /*
+ * Set Control VDAT Reference Voltage - 0.325V and
+ * Control VSRC Reference Voltage - 0.6V
+ */
+ reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
+ reg &= ~(VDAT_MASK | VSRC_MASK);
+ reg |= (VDAT_VAL << VDAT_OFFSET) | (VSRC_VAL << VSRC_OFFSET);
+ writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
+}
+
+static int mvebu_cp110_utmi_phy_power_off(struct phy *phy)
+{
+ struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
+ struct mvebu_cp110_utmi *utmi = port->priv;
+ int i;
+
+ /* Power down UTMI PHY port */
+ regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
+ UTMI_PHY_CFG_PU_MASK);
+
+ for (i = 0; i < UTMI_PHY_PORTS; i++) {
+ int test = regmap_test_bits(utmi->syscon,
+ SYSCON_UTMI_CFG_REG(i),
+ UTMI_PHY_CFG_PU_MASK);
+ /* skip PLL shutdown if there are active UTMI PHY ports */
+ if (test != 0)
+ return 0;
+ }
+
+ /* PLL Power down if all UTMI PHYs are down */
+ regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
+
+ return 0;
+}
+
+static int mvebu_cp110_utmi_phy_power_on(struct phy *phy)
+{
+ struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
+ struct mvebu_cp110_utmi *utmi = port->priv;
+ struct device *dev = &phy->dev;
+ int ret;
+ u32 reg;
+
+ /* It is necessary to power off UTMI before configuration */
+ ret = mvebu_cp110_utmi_phy_power_off(phy);
+ if (ret) {
+ dev_err(dev, "UTMI power OFF before power ON failed\n");
+ return ret;
+ }
+
+ /*
+ * If UTMI port is connected to USB Device controller,
+ * configure the USB MUX prior to UTMI PHY initialization.
+ * The single USB device controller can be connected
+ * to UTMI0 or to UTMI1 PHY port, but not to both.
+ */
+ if (port->device_mode) {
+ regmap_update_bits(utmi->syscon, SYSCON_USB_CFG_REG,
+ USB_CFG_DEVICE_EN_MASK | USB_CFG_DEVICE_MUX_MASK,
+ USB_CFG_DEVICE_EN_MASK |
+ (port->id << USB_CFG_DEVICE_MUX_OFFSET));
+ }
+
+ /* Set Test suspendm mode and enable Test UTMI select */
+ reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+ reg |= SUSPENDM | TEST_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+
+ /* Wait for UTMI power down */
+ mdelay(1);
+
+ /* PHY port setup first */
+ mvebu_cp110_utmi_port_setup(port);
+
+ /* Power UP UTMI PHY */
+ regmap_set_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
+ UTMI_PHY_CFG_PU_MASK);
+
+ /* Disable Test UTMI select */
+ reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+ reg &= ~TEST_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+
+ /* Wait for impedance calibration */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
+ reg & IMPCAL_DONE,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "Failed to end UTMI impedance calibration\n");
+ return ret;
+ }
+
+ /* Wait for PLL calibration */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
+ reg & PLLCAL_DONE,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "Failed to end UTMI PLL calibration\n");
+ return ret;
+ }
+
+ /* Wait for PLL ready */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg,
+ reg & PLL_RDY,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "PLL is not ready\n");
+ return ret;
+ }
+
+ /* PLL Power up */
+ regmap_set_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
+
+ return 0;
+}
+
+static const struct phy_ops mvebu_cp110_utmi_phy_ops = {
+ .power_on = mvebu_cp110_utmi_phy_power_on,
+ .power_off = mvebu_cp110_utmi_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id mvebu_cp110_utmi_of_match[] = {
+ { .compatible = "marvell,cp110-utmi-phy" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mvebu_cp110_utmi_of_match);
+
+static int mvebu_cp110_utmi_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mvebu_cp110_utmi *utmi;
+ struct phy_provider *provider;
+ struct device_node *child;
+ u32 usb_devices = 0;
+
+ utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return -ENOMEM;
+
+ utmi->dev = dev;
+
+ /* Get system controller region */
+ utmi->syscon = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "marvell,system-controller");
+ if (IS_ERR(utmi->syscon)) {
+ dev_err(dev, "Missing UTMI system controller\n");
+ return PTR_ERR(utmi->syscon);
+ }
+
+ /* Get UTMI memory region */
+ utmi->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(utmi->regs))
+ return PTR_ERR(utmi->regs);
+
+ for_each_available_child_of_node(dev->of_node, child) {
+ struct mvebu_cp110_utmi_port *port;
+ struct phy *phy;
+ int ret;
+ u32 val;
+
+ ret = of_property_read_u32(child, "reg", &val);
+ if (ret < 0) {
+ dev_err(dev, "missing 'reg' property (%d)\n", ret);
+ continue;
+ }
+
+ if (val >= UTMI_PHY_PORTS) {
+ dev_err(dev, "invalid 'reg' property\n");
+ continue;
+ }
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ port->device_mode = false;
+ if (of_property_read_bool(child, "marvell,cp110-utmi-device-mode")) {
+ usb_devices++;
+ if (usb_devices > 1)
+ dev_err(dev,
+ "Single USB device allowed! Port%d set as host\n", val);
+ else
+ port->device_mode = true;
+ }
+
+ /* Retrieve PHY capabilities */
+ utmi->ops = &mvebu_cp110_utmi_phy_ops;
+
+ /* Instantiate the PHY */
+ phy = devm_phy_create(dev, child, utmi->ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "Failed to create the UTMI PHY\n");
+ of_node_put(child);
+ return PTR_ERR(phy);
+ }
+
+ port->priv = utmi;
+ port->id = val;
+ phy_set_drvdata(phy, port);
+
+ /* Ensure the PHY is powered off */
+ mvebu_cp110_utmi_phy_power_off(phy);
+ }
+
+ dev_set_drvdata(dev, utmi);
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver mvebu_cp110_utmi_driver = {
+ .probe = mvebu_cp110_utmi_phy_probe,
+ .driver = {
+ .name = "mvebu-cp110-utmi-phy",
+ .of_match_table = mvebu_cp110_utmi_of_match,
+ },
+};
+module_platform_driver(mvebu_cp110_utmi_driver);
+
+MODULE_AUTHOR("Konstatin Porotchkin <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada CP110 UTMI PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add DTS binding for Marvell CP110 UTMI driver
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 69 ++++++++++++++++++--
1 file changed, 63 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
index aa99ceec73b0..109888ba9d2d 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
@@ -1,30 +1,61 @@
-MVEBU A3700 UTMI PHY
---------------------
+MVEBU UTMI PHY
+---------------
USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 3700
+* Armada 7k/8k (on the CP110)
+* Armada CN913x (on the CP115)
On Armada 3700, there are two USB controllers, one is compatible with the USB2
and USB3 specifications and supports OTG. The other one is USB2 compliant and
only supports host mode. Both of these controllers come with a slightly
different UTMI PHY.
+On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
+Each of two exiting UTMI PHYs could be connected to either USB host or USB device
+controller.
+The USB device controller can only be connected to a single UTMI PHY port:
+ 0.H----- USB HOST0
+UTMI PHY0 --------/
+ 0.D-----0
+ \------ USB DEVICE
+ 1.D-----1
+UTMI PHY1 --------\
+ 1.H----- USB HOST1
+
+
Required Properties:
- compatible: Should be one of:
* "marvell,a3700-utmi-host-phy" for the PHY connected to
- the USB2 host-only controller.
+ the USB2 host-only controller (for Armada3700 only).
* "marvell,a3700-utmi-otg-phy" for the PHY connected to
- the USB3 and USB2 OTG capable controller.
+ the USB3 and USB2 OTG capable controller (for Armada3700 only.
+ * "marvell,cp110-utmi-phy" (for Armada 7k/8k or CN913x only).
- reg: PHY IP register range.
- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
region covering registers related to both the host
- controller and the PHY.
-- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
+ controller and the PHY (for Armada3700 only).
+- marvell,system-controller: should contain a phandle to the system
+ controller node (for Armada 7k/8k or CN913x only)
+- #phy-cells: Standard property (Documentation: phy-bindings.txt.
+ Should be 0 (for Armada3700 only).
+
+
+Required properties (child nodes, for Armada 7k/8k/CN913x only):
+
+- reg: UTMI PHY port ID (0 or 1).
+- #phy-cells : Should be 0.
+
+
+Optional Properties (child nodes, for Armada 7k/8k/CN913x only)::
+- marvell,cp110-utmi-device-mode: request the driver to connect the UTMI PHY
+ port to USB device controller.
Example:
+Armada3700
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
@@ -36,3 +67,29 @@ Example:
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};
+
+Armada 7k/8k/CN913x
+
+ CP11X_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x580000 0x2000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): phy@0 {
+ /* UTMI PHY port-0 is connected to USB Host controller-0 */
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): phy@1 {
+ /* UTMI PHY port-1 is connected to USB device controller */
+ reg = <1>;
+ #phy-cells = <0>;
+ marvell,cp110-utmi-device-mode;
+ };
+ };
+
+
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add support for Marvell CP110 UTMI driver in a common DTSI
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 994a2fce449a..5f1f5d51c881 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -275,6 +275,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x580000 0x2000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
On Fri, Jan 29, 2021 at 10:07:13AM +0000, Russell King - ARM Linux admin wrote:
> On Fri, Jan 29, 2021 at 10:28:49AM +0100, Lubomir Rintel wrote:
> > > + /*
> > > + * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
> > > + * See the functional specification for details.
> >
> > I tried to, couldn't find it. Perhaps you could elaborate more here, or
> > include a link in the header.
>
> Marvell documents are generally not publically available. This is the
> case here.
In that case the "elaborate more" part applies, otherwise the comment
remains rather meaningless. Perhaps it wouldn't be too difficult to
clarify things with an extra sentence or two without revealing any
secrets.
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Take care
Lubo
Hello, Lubomir,
Thank you for your review!
> > +static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port
> > +*port) {
> > + u32 reg;
> > +
> > + /*
> > + * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
> > + * See the functional specification for details.
>
> I tried to, couldn't find it. Perhaps you could elaborate more here, or include a
> link in the header.
[KP] This is the frequency of a quartz resonator connected to REFCLK_XIN/REFCLK_XOUT SoC pins.
The default crystal frequency used now at all Marvell reference platforms is 25MHz.
The default out of reset state register values are however have settings for 40MHz crystal used at the time of RTL code freeze.
I will mention this fact in the second patch version.
>
> > + /* PLL Power down if all UTMI PHYs are down */
> > + regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG,
> > +USB_CFG_PLL_MASK);
> > +
> > + return 0;
> > +}
> > +
> > +static int mvebu_cp110_utmi_phy_power_on(struct phy *phy) {
> > + struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
> > + struct mvebu_cp110_utmi *utmi = port->priv;
> > + struct device *dev = &phy->dev;
> > + int ret;
> > + u32 reg;
> > +
> > + /* It is necessary to power off UTMI before configuration */
> > + ret = mvebu_cp110_utmi_phy_power_off(phy);
>
> mvebu_cp110_utmi_phy_power_off() also sometimes, but not always, shuts
> down the PLL. Is that necessary? I guess all you care about is the bit in
> UTMI_PHY_CFG_PU_MASK?
[KP] Not sure I fully understand the question. Both UTMI PHYs are using the same dedicated PLL source.
I am trying to save the power to shutting down this PLL when both PHY ports are down.
>
> > +
> > + ret = of_property_read_u32(child, "reg", &val);
> > + if (ret < 0) {
> > + dev_err(dev, "missing 'reg' property (%d)\n", ret);
>
> A nit: the property is not necessarily missing -- it could be malformed (with ret
> of -ENODATA or -EOVERFLOW).
>
> Also, perhaps you want to log the name of node that has problems ("%pOF",
> child); also in the error messages below.
[KP] OK, will do it in the second patch version.
>
> > + continue;
> > + }
> > +
> > + if (val >= UTMI_PHY_PORTS) {
> > + dev_err(dev, "invalid 'reg' property\n");
> > + continue;
> > + }
>
> Perhaps you could just squelch those two warnings together:
>
>
> if (ret || val >= UTMI_PHY_PORTS) {
> dev_err(dev, "invalid 'reg' property on %pOF\n", child);
> continue;
> }
>
[KP] Yes, it will definitely be better, thank you.
> > --
> > 2.17.1
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__lists.infradead.org_mailman_listinfo_linux-2Darm-
> 2Dkernel&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=-
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> L7ZXEX4MPsfaMtPDu87RltnvXa90&e=
Hi, Lubomir,
Thank you for your review!
> On Wed, Jan 27, 2021 at 01:27:17PM +0200, [email protected] wrote:
> > From: Konstantin Porotchkin <[email protected]>
> >
> > Add DTS binding for Marvell CP110 UTMI driver
> >
> > Signed-off-by: Konstantin Porotchkin <[email protected]>
>
> Any chance you could convert the document to YAML so that it could be used
> for automatic validation?
>
[KP] I believe it is possible, but probably should be done by a separate patch.
Here I am extending the existing documentation.
> > ---
> > Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 69
> > ++++++++++++++++++--
> > 1 file changed, 63 insertions(+), 6 deletions(-)
...
> > Required Properties:
> >
> > - compatible: Should be one of:
> > * "marvell,a3700-utmi-host-phy" for the PHY connected to
> > - the USB2 host-only controller.
> > + the USB2 host-only controller (for Armada3700 only).
> > * "marvell,a3700-utmi-otg-phy" for the PHY connected to
> > - the USB3 and USB2 OTG capable controller.
> > + the USB3 and USB2 OTG capable controller (for Armada3700 only.
> > + * "marvell,cp110-utmi-phy" (for Armada 7k/8k or CN913x only).
> > - reg: PHY IP register range.
> > - marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
> > region covering registers related to both the host
> > - controller and the PHY.
> > -- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be
> 0.
> > + controller and the PHY (for Armada3700 only).
> > +- marvell,system-controller: should contain a phandle to the system
> > + controller node (for Armada 7k/8k or CN913x only)
>
> I guess this is okay, but referring to a syscon is done in a multitude ways across
> various other bindings; with the most popular being just:
>
> syscon = <&syscon>;
>
> Perhaps consider doing that?
[KP] I was not sure that I can use a generic name inside the PHY entry
if it is not defined as part of the generic PHY properties.
I just did not see a good example of such in PHY bindings documentation.
If it is legal, I can change this entry name to just "syscon".
>
> > +- #phy-cells: Standard property (Documentation: phy-bindings.txt.
> > + Should be 0 (for Armada3700 only).
> > +
> > +
> > +Required properties (child nodes, for Armada 7k/8k/CN913x only):
> > +
> > +- reg: UTMI PHY port ID (0 or 1).
> > +- #phy-cells : Should be 0.
> > +
> > +
> > +Optional Properties (child nodes, for Armada 7k/8k/CN913x only)::
> >
> > +- marvell,cp110-utmi-device-mode: request the driver to connect the UTMI
> PHY
> > + port to USB device controller.
>
> Do you need a separate property for this? Could the driver look at "dr_mode"
> property of the USB controller node to see if it's supposed to be in
> device/peripheral mode?
[KP] Yes, it seems I missed this option. I will try to change the code to support it in version 2.
>
> > Example:
> >
> > +Armada3700
> > usb2_utmi_host_phy: phy@5f000 {
> > compatible = "marvell,armada-3700-utmi-host-phy";
> > reg = <0x5f000 0x800>;
> > @@ -36,3 +67,29 @@ Example:
> > --
> > 2.17.1
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
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