https://lore.kernel.org/linux-clk/[email protected]/
Changelog v2 -> v3:
* added HAS_IOMEM || COMPILE_TEST and OF dependencies to driver in
Kconfig
* added patch 'clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand'
Alexandru Ardelean (4):
clk: axi-clkgen: replace ARCH dependencies with driver deps
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP
support
clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
.../devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 +
drivers/clk/Kconfig | 3 ++-
drivers/clk/clk-axi-clkgen.c | 15 ++++++++++++---
3 files changed, 15 insertions(+), 4 deletions(-)
--
2.17.1
No major functional change. Noticed while checking the driver code that
this could be used.
Saves two lines.
Signed-off-by: Alexandru Ardelean <[email protected]>
---
drivers/clk/clk-axi-clkgen.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index 9d1b0fc56c73..ac6ff736ac8f 100644
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -510,7 +510,6 @@ static int axi_clkgen_probe(struct platform_device *pdev)
struct clk_init_data init;
const char *parent_names[2];
const char *clk_name;
- struct resource *mem;
unsigned int i;
int ret;
@@ -522,8 +521,7 @@ static int axi_clkgen_probe(struct platform_device *pdev)
if (!axi_clkgen)
return -ENOMEM;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
+ axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(axi_clkgen->base))
return PTR_ERR(axi_clkgen->base);
--
2.17.1
The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
driver needs to use different PFD & VCO limits.
For ZynqMP, these needs to be selected by using the
'adi,zynqmp-axi-clkgen-2.00.a' string.
Signed-off-by: Alexandru Ardelean <[email protected]>
---
Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
index 0d06387184d6..983033fe5b17 100644
--- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
+++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
@@ -20,6 +20,7 @@ properties:
compatible:
enum:
- adi,axi-clkgen-2.00.a
+ - adi,zynqmp-axi-clkgen-2.00.a
clocks:
description:
--
2.17.1
The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).
Signed-off-by: Dragos Bogdan <[email protected]>
Signed-off-by: Alexandru Ardelean <[email protected]>
---
drivers/clk/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..cee1d4e657bc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,8 @@ config CLK_TWL6040
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
- depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
+ depends on HAS_IOMEM || COMPILE_TEST
+ depends on OF
help
Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
FPGAs. It is commonly used in Analog Devices' reference designs.
--
2.17.1
For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
support these, this change adds a compatible string (i.e.
'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these
limits and apply them.
Signed-off-by: Dragos Bogdan <[email protected]>
Signed-off-by: Mathias Tausen <[email protected]>
Signed-off-by: Alexandru Ardelean <[email protected]>
---
drivers/clk/clk-axi-clkgen.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index ad86e031ba3e..9d1b0fc56c73 100644
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -108,6 +108,13 @@ static uint32_t axi_clkgen_lookup_lock(unsigned int m)
return 0x1f1f00fa;
}
+static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
+ .fpfd_min = 10000,
+ .fpfd_max = 450000,
+ .fvco_min = 800000,
+ .fvco_max = 1600000,
+};
+
static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
.fpfd_min = 10000,
.fpfd_max = 300000,
@@ -560,6 +567,10 @@ static int axi_clkgen_remove(struct platform_device *pdev)
}
static const struct of_device_id axi_clkgen_ids[] = {
+ {
+ .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
+ .data = &axi_clkgen_zynqmp_default_limits,
+ },
{
.compatible = "adi,axi-clkgen-2.00.a",
.data = &axi_clkgen_zynq_default_limits,
--
2.17.1
On 2/1/21 4:12 PM, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
>
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
>
> Signed-off-by: Dragos Bogdan <[email protected]>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> ---
> drivers/clk/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 85856cff506c..cee1d4e657bc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -247,7 +247,8 @@ config CLK_TWL6040
>
> config COMMON_CLK_AXI_CLKGEN
> tristate "AXI clkgen driver"
> - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> + depends on HAS_IOMEM || COMPILE_TEST
> + depends on OF
> help
> Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> FPGAs. It is commonly used in Analog Devices' reference designs.
>
Make sense.
Acked-by: Michal Simek <[email protected]>
Thanks,
Michal
On Mon, Feb 01, 2021 at 05:12:42PM +0200, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
>
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
>
> Signed-off-by: Dragos Bogdan <[email protected]>
> Signed-off-by: Alexandru Ardelean <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
> ---
> drivers/clk/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 85856cff506c..cee1d4e657bc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -247,7 +247,8 @@ config CLK_TWL6040
>
> config COMMON_CLK_AXI_CLKGEN
> tristate "AXI clkgen driver"
> - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> + depends on HAS_IOMEM || COMPILE_TEST
> + depends on OF
> help
> Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> FPGAs. It is commonly used in Analog Devices' reference designs.
> --
> 2.17.1
>
Thanks,
Moritz
On Mon, Feb 01, 2021 at 05:12:43PM +0200, Alexandru Ardelean wrote:
> For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
> support these, this change adds a compatible string (i.e.
> 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these
> limits and apply them.
>
> Signed-off-by: Dragos Bogdan <[email protected]>
> Signed-off-by: Mathias Tausen <[email protected]>
> Signed-off-by: Alexandru Ardelean <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
> ---
> drivers/clk/clk-axi-clkgen.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
> index ad86e031ba3e..9d1b0fc56c73 100644
> --- a/drivers/clk/clk-axi-clkgen.c
> +++ b/drivers/clk/clk-axi-clkgen.c
> @@ -108,6 +108,13 @@ static uint32_t axi_clkgen_lookup_lock(unsigned int m)
> return 0x1f1f00fa;
> }
>
> +static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
> + .fpfd_min = 10000,
> + .fpfd_max = 450000,
> + .fvco_min = 800000,
> + .fvco_max = 1600000,
> +};
> +
> static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
> .fpfd_min = 10000,
> .fpfd_max = 300000,
> @@ -560,6 +567,10 @@ static int axi_clkgen_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id axi_clkgen_ids[] = {
> + {
> + .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
> + .data = &axi_clkgen_zynqmp_default_limits,
> + },
> {
> .compatible = "adi,axi-clkgen-2.00.a",
> .data = &axi_clkgen_zynq_default_limits,
> --
> 2.17.1
>
Quoting Alexandru Ardelean (2021-02-01 07:12:43)
> For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
> support these, this change adds a compatible string (i.e.
> 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these
> limits and apply them.
>
> Signed-off-by: Dragos Bogdan <[email protected]>
> Signed-off-by: Mathias Tausen <[email protected]>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> ---
Applied to clk-next
Quoting Alexandru Ardelean (2021-02-01 07:12:42)
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
>
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
>
> Signed-off-by: Dragos Bogdan <[email protected]>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> ---
Applied to clk-next
Quoting Alexandru Ardelean (2021-02-01 07:12:44)
> The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
> driver needs to use different PFD & VCO limits.
>
> For ZynqMP, these needs to be selected by using the
> 'adi,zynqmp-axi-clkgen-2.00.a' string.
>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> ---
Applied to clk-next
Quoting Alexandru Ardelean (2021-02-01 07:12:45)
> No major functional change. Noticed while checking the driver code that
> this could be used.
> Saves two lines.
>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> ---
Applied to clk-next