Protection Keys for Supervisor Pages(PKS) is a feature that extends the
Protection Keys architecture to support thread-specific permission
restrictions on supervisor pages.
PKS works similar to an existing feature named PKU(protecting user pages).
They both perform an additional check after all legacy access
permissions checks are done. If violated, #PF occurs and PFEC.PK bit will
be set. PKS introduces MSR IA32_PKRS to manage supervisor protection key
rights. The MSR contains 16 pairs of ADi and WDi bits. Each pair
advertises on a group of pages with the same key which is set in the
leaf paging-structure entries(bits[62:59]). Currently, IA32_PKRS is not
supported by XSAVES architecture.
This patchset aims to add the virtualization of PKS in KVM. It
implemented PKS CPUID enumeration, vmentry/vmexit configuration, MSR
exposure, nested supported etc. Currently, PKS is not yet supported for
shadow paging.
PKS bare metal support:
https://lore.kernel.org/lkml/[email protected]/
Detailed information about PKS can be found in the latest Intel 64 and
IA-32 Architectures Software Developer's Manual.
---
Changelogs:
v3->v4
- Make the MSR intercept and load-controls setting depend on CR4.PKS value
- shadow the guest pkrs and make it usable in PKS emultion
- add the cr4_pke and cr4_pks check in pkr_mask update
- squash PATCH 2 and PATCH 5 to make the dependencies read more clear
- v3: https://lore.kernel.org/lkml/[email protected]/
v2->v3:
- No function changes since last submit
- rebase on the latest PKS kernel support:
https://lore.kernel.org/lkml/[email protected]/
- add MSR_IA32_PKRS to the vmx_possible_passthrough_msrs[]
- RFC v2: https://lore.kernel.org/lkml/[email protected]/
v1->v2:
- rebase on the latest PKS kernel support:
https://github.com/weiny2/linux-kernel/tree/pks-rfc-v3
- add a kvm-unit-tests for PKS
- add the check in kvm_init_msr_list for PKRS
- place the X86_CR4_PKS in mmu_role_bits in kvm_set_cr4
- add the support to expose VM_{ENTRY, EXIT}_LOAD_IA32_PKRS in nested
VMX MSR
- RFC v1: https://lore.kernel.org/lkml/[email protected]/
---
Chenyi Qiang (5):
KVM: VMX: Introduce PKS VMCS fields
KVM: X86: Expose PKS to guest
KVM: MMU: Rename the pkru to pkr
KVM: MMU: Add support for PKS emulation
KVM: VMX: Enable PKS for nested VM
arch/x86/include/asm/kvm_host.h | 17 +++---
arch/x86/include/asm/pkeys.h | 1 +
arch/x86/include/asm/vmx.h | 6 ++
arch/x86/kvm/cpuid.c | 3 +-
arch/x86/kvm/mmu.h | 23 ++++----
arch/x86/kvm/mmu/mmu.c | 81 +++++++++++++++------------
arch/x86/kvm/vmx/capabilities.h | 6 ++
arch/x86/kvm/vmx/nested.c | 38 ++++++++++++-
arch/x86/kvm/vmx/vmcs.h | 1 +
arch/x86/kvm/vmx/vmcs12.c | 2 +
arch/x86/kvm/vmx/vmcs12.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 99 +++++++++++++++++++++++++++++++--
arch/x86/kvm/vmx/vmx.h | 1 +
arch/x86/kvm/x86.c | 11 +++-
arch/x86/kvm/x86.h | 8 +++
arch/x86/mm/pkeys.c | 6 ++
include/linux/pkeys.h | 4 ++
17 files changed, 249 insertions(+), 64 deletions(-)
--
2.17.1
On 05/02/21 09:37, Chenyi Qiang wrote:
> Protection Keys for Supervisor Pages(PKS) is a feature that extends the
> Protection Keys architecture to support thread-specific permission
> restrictions on supervisor pages.
>
> PKS works similar to an existing feature named PKU(protecting user pages).
> They both perform an additional check after all legacy access
> permissions checks are done. If violated, #PF occurs and PFEC.PK bit will
> be set. PKS introduces MSR IA32_PKRS to manage supervisor protection key
> rights. The MSR contains 16 pairs of ADi and WDi bits. Each pair
> advertises on a group of pages with the same key which is set in the
> leaf paging-structure entries(bits[62:59]). Currently, IA32_PKRS is not
> supported by XSAVES architecture.
>
> This patchset aims to add the virtualization of PKS in KVM. It
> implemented PKS CPUID enumeration, vmentry/vmexit configuration, MSR
> exposure, nested supported etc. Currently, PKS is not yet supported for
> shadow paging.
>
> PKS bare metal support:
> https://lore.kernel.org/lkml/[email protected]/
>
> Detailed information about PKS can be found in the latest Intel 64 and
> IA-32 Architectures Software Developer's Manual.
>
> ---
>
> Changelogs:
>
> v3->v4
> - Make the MSR intercept and load-controls setting depend on CR4.PKS value
> - shadow the guest pkrs and make it usable in PKS emultion
> - add the cr4_pke and cr4_pks check in pkr_mask update
> - squash PATCH 2 and PATCH 5 to make the dependencies read more clear
> - v3: https://lore.kernel.org/lkml/[email protected]/
>
> v2->v3:
> - No function changes since last submit
> - rebase on the latest PKS kernel support:
> https://lore.kernel.org/lkml/[email protected]/
> - add MSR_IA32_PKRS to the vmx_possible_passthrough_msrs[]
> - RFC v2: https://lore.kernel.org/lkml/[email protected]/
>
> v1->v2:
> - rebase on the latest PKS kernel support:
> https://github.com/weiny2/linux-kernel/tree/pks-rfc-v3
> - add a kvm-unit-tests for PKS
> - add the check in kvm_init_msr_list for PKRS
> - place the X86_CR4_PKS in mmu_role_bits in kvm_set_cr4
> - add the support to expose VM_{ENTRY, EXIT}_LOAD_IA32_PKRS in nested
> VMX MSR
> - RFC v1: https://lore.kernel.org/lkml/[email protected]/
>
> ---
>
> Chenyi Qiang (5):
> KVM: VMX: Introduce PKS VMCS fields
> KVM: X86: Expose PKS to guest
> KVM: MMU: Rename the pkru to pkr
> KVM: MMU: Add support for PKS emulation
> KVM: VMX: Enable PKS for nested VM
>
> arch/x86/include/asm/kvm_host.h | 17 +++---
> arch/x86/include/asm/pkeys.h | 1 +
> arch/x86/include/asm/vmx.h | 6 ++
> arch/x86/kvm/cpuid.c | 3 +-
> arch/x86/kvm/mmu.h | 23 ++++----
> arch/x86/kvm/mmu/mmu.c | 81 +++++++++++++++------------
> arch/x86/kvm/vmx/capabilities.h | 6 ++
> arch/x86/kvm/vmx/nested.c | 38 ++++++++++++-
> arch/x86/kvm/vmx/vmcs.h | 1 +
> arch/x86/kvm/vmx/vmcs12.c | 2 +
> arch/x86/kvm/vmx/vmcs12.h | 6 +-
> arch/x86/kvm/vmx/vmx.c | 99 +++++++++++++++++++++++++++++++--
> arch/x86/kvm/vmx/vmx.h | 1 +
> arch/x86/kvm/x86.c | 11 +++-
> arch/x86/kvm/x86.h | 8 +++
> arch/x86/mm/pkeys.c | 6 ++
> include/linux/pkeys.h | 4 ++
> 17 files changed, 249 insertions(+), 64 deletions(-)
>
Looks mostly good, but I'll only be able to include it after the bare
metal implementation is in.
Paolo