2021-02-08 12:08:48

by Amelie Delaunay

Subject: [PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider

STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.

This series registers the usbphyc as clock provider of this ck_usbo_48m clock.

---
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

.../bindings/phy/phy-stm32-usbphyc.yaml | 5 ++
drivers/phy/st/Kconfig | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 65 +++++++++++++++++++
3 files changed, 71 insertions(+)

--
2.17.1

2021-02-08 12:09:13

by Amelie Delaunay

Subject: [PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property

usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Amelie Delaunay <[email protected]>
---
Changes in v3:
- remove #clock-cells from required properties
---
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..018cc1246ee1 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
vdda1v8-supply:
description: regulator providing 1V8 power supply to the PLL block

+ '#clock-cells':
+ description: number of clock cells for ck_usbo_48m consumer
+ const: 0
+
#Required child nodes:

patternProperties:
@@ -120,6 +124,7 @@ examples:
vdda1v8-supply = <&reg18>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <0>;

usbphyc_port0: usb-phy@0 {
reg = <0>;
--
2.17.1

2021-02-10 20:23:20

by Rob Herring (Arm)

Subject: Re: [PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property

On Mon, 08 Feb 2021 12:46:58 +0100, Amelie Delaunay wrote:
> usbphyc provides a unique clock called ck_usbo_48m.
> STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
> ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
>
> ck_usbo_48m is available as soon as the PLL is enabled.
>
> Signed-off-by: Amelie Delaunay <[email protected]>
> ---
> Changes in v3:
> - remove #clock-cells from required properties
> ---
> Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>

Acked-by: Rob Herring <[email protected]>