2021-02-03 08:45:28

by Irui Wang (王瑞)

Subject: [PATCH 3/5] dt-bindings: media: mtk-vcodec: Add binding for MT8192 VENC

Updates binding document for mt8192 encoder driver.

Signed-off-by: Irui Wang <[email protected]>
---
.../bindings/media/mediatek-vcodec.txt | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
index e4644f8caee9..c7fac557006f 100644
--- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -9,6 +9,7 @@ Required properties:
"mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder.
"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
+ "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
- reg : Physical base address of the video codec registers and length of
memory mapped region.
- interrupts : interrupt number to the cpu.
@@ -128,3 +129,28 @@ vcodec_enc_lt: vcodec@19002000 {
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
};
+
+vcodec_enc: vcodec@0x17020000 {
+ compatible = "mediatek,mt8192-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+ <&iommu0 M4U_PORT_L7_VENC_REC>,
+ <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ mediatek,scp = <&scp>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc-set1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+};
+
--
2.25.1

2021-02-10 23:02:14

by Rob Herring (Arm)

Subject: Re: [PATCH 3/5] dt-bindings: media: mtk-vcodec: Add binding for MT8192 VENC

On Wed, Feb 03, 2021 at 04:37:50PM +0800, Irui Wang wrote:
> Updates binding document for mt8192 encoder driver.
>
> Signed-off-by: Irui Wang <[email protected]>
> ---
> .../bindings/media/mediatek-vcodec.txt | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> index e4644f8caee9..c7fac557006f 100644
> --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> @@ -9,6 +9,7 @@ Required properties:
> "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder.
> "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
> "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
> + "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
> - reg : Physical base address of the video codec registers and length of
> memory mapped region.
> - interrupts : interrupt number to the cpu.
> @@ -128,3 +129,28 @@ vcodec_enc_lt: vcodec@19002000 {
> assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
> assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
> };
> +
> +vcodec_enc: vcodec@0x17020000 {

Don't add an example just for a new compatible.

> + compatible = "mediatek,mt8192-vcodec-enc";
> + reg = <0 0x17020000 0 0x2000>;
> + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> + <&iommu0 M4U_PORT_L7_VENC_REC>,
> + <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + mediatek,scp = <&scp>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_VENC>;
> + clocks = <&vencsys CLK_VENC_SET1_VENC>;
> + clock-names = "venc-set1";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +};
> +
> --
> 2.25.1
>