2021-02-12 03:02:40

by Nobuhiro Iwamatsu

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Subject: [PATCH v2 4/4] arm: dts: visconti: Add DT support for Toshiba Visconti5 ethernet controller

Add the ethernet controller node in Toshiba Visconti5 SoC-specific DT file.
And enable this node in TMPV7708 RM main board's board-specific DT file.

Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
.../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 18 ++++++++++++++
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 24 +++++++++++++++++++
2 files changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
index ed0bf7f13f54..48fa8776e36f 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
@@ -41,3 +41,21 @@ &uart1 {
clocks = <&uart_clk>;
clock-names = "apb_pclk";
};
+
+&piether {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ clocks = <&clk300mhz>, <&clk125mhz>;
+ clock-names = "stmmaceth", "phy_ref_clk";
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 242f25f4e12a..fabb8d66ef93 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -134,6 +134,20 @@ uart_clk: uart-clk {
#clock-cells = <0>;
};

+ clk125mhz: clk125mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clk125mhz";
+ };
+
+ clk300mhz: clk300mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clk300mhz";
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -384,6 +398,16 @@ spi6: spi@28146000 {
#size-cells = <0>;
status = "disabled";
};
+
+ piether: ethernet@28000000 {
+ compatible = "toshiba,visconti-dwmac";
+ reg = <0 0x28000000 0 0x10000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ snps,txpbl = <4>;
+ snps,rxpbl = <4>;
+ status = "disabled";
+ };
};
};

--
2.30.0.rc2


2021-02-12 09:36:47

by Arnd Bergmann

[permalink] [raw]
Subject: Re: [PATCH v2 4/4] arm: dts: visconti: Add DT support for Toshiba Visconti5 ethernet controller

On Fri, Feb 12, 2021 at 4:03 AM Nobuhiro Iwamatsu
<[email protected]> wrote:
> @@ -384,6 +398,16 @@ spi6: spi@28146000 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + piether: ethernet@28000000 {
> + compatible = "toshiba,visconti-dwmac";

Shouldn't there be a more specific compatible string here, as well as the
particular version of the dwmac you use?

In the binding example, you list the device as "dma-coherent",
but in this instance, it is not marked that way. Can you find out
whether the device is in fact connected properly to a cache-coherent
bus?

Note that failing to mark it as cache-coherent will make the device
rather slow and possibly not work correctly if it is in fact coherent,
but the default is non-coherent since a lot of SoCs are lacking
that hardware support.

Arnd

2021-02-12 15:04:34

by Nobuhiro Iwamatsu

[permalink] [raw]
Subject: Re: [PATCH v2 4/4] arm: dts: visconti: Add DT support for Toshiba Visconti5 ethernet controller

Hi,

Thanks for your review.

On Fri, Feb 12, 2021 at 10:32:09AM +0100, Arnd Bergmann wrote:
> On Fri, Feb 12, 2021 at 4:03 AM Nobuhiro Iwamatsu
> <[email protected]> wrote:
> > @@ -384,6 +398,16 @@ spi6: spi@28146000 {
> > #size-cells = <0>;
> > status = "disabled";
> > };
> > +
> > + piether: ethernet@28000000 {
> > + compatible = "toshiba,visconti-dwmac";
>
> Shouldn't there be a more specific compatible string here, as well as the
> particular version of the dwmac you use?

I rechecked the code again based on your point.
I need to specify the version of dwmac. I also noticed that it could
remove some unnecessary code. I will fix this.

>
> In the binding example, you list the device as "dma-coherent",
> but in this instance, it is not marked that way. Can you find out
> whether the device is in fact connected properly to a cache-coherent
> bus?
>
> Note that failing to mark it as cache-coherent will make the device
> rather slow and possibly not work correctly if it is in fact coherent,
> but the default is non-coherent since a lot of SoCs are lacking
> that hardware support.

Thanks for point out.
This hardware does not require dma-coherent. I will remove dma-coherent from DT
binding document.

>
> Arnd
>

Best regards,
Nobuhiro