2021-03-04 06:20:22

by Dmitry Osipenko

[permalink] [raw]

Subject: [PATCH v4 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path

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The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.

Tested-by: Peter Geis <[email protected]> # Ouya T30
Tested-by: Nicolas Chauvet <[email protected]> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <[email protected]> # Ouya T30
Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index df9a5ca8c99c..fd2ba3c59178 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -638,7 +638,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,

err = tegra_powergate_enable_clocks(pg);
if (err)
- goto disable_clks;
+ goto powergate_off;

usleep_range(10, 20);

--
2.29.2

2021-03-25 14:28:33

by Thierry Reding

[permalink] [raw]

Subject: Re: [PATCH v4 1/5] soc/tegra: pmc: Fix imbalanced clock disabling in error code path

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On Tue, Mar 02, 2021 at 03:24:58PM +0300, Dmitry Osipenko wrote:
> The tegra_powergate_power_up() has a typo in the error code path where it
> will try to disable clocks twice, fix it. In practice that error never
> happens, so this is a minor correction.
>
> Tested-by: Peter Geis <[email protected]> # Ouya T30
> Tested-by: Nicolas Chauvet <[email protected]> # PAZ00 T20 and TK1 T124
> Tested-by: Matt Merhar <[email protected]> # Ouya T30
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---
> drivers/soc/tegra/pmc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

Thierry

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