This patch series adds support for two Ethernet ports on Allwinner R40.
R40 (aka V40,A40i,T3) has two different Ethernet IPs called EMAC and GMAC.
EMAC only support 10/100 Mbit in MII mode, while GMAC support both 10/100
(MII) and 10/100/1000 (RGMII).
In contrast to A10/A20 where GMAC and EMAC share the same pins making EMAC
somewhat pointless, on R40 EMAC can be routed to port H.
Both EMAC (on port H) and GMAC (on port A) can be then enabled at the same
time, allowing for two ethernet ports.
Evgeny Boger (2):
net: allwinner: reset control support
dts: r40: add second ethernet support
arch/arm/boot/dts/sun8i-r40.dtsi | 53 +++++++++++++++++++++
drivers/net/ethernet/allwinner/sun4i-emac.c | 21 +++++++-
2 files changed, 73 insertions(+), 1 deletion(-)
--
2.17.1
R40 (aka V40/A40i/T3) and A10/A20 share the same EMAC IP.
However, on R40 the EMAC is gated by default.
Signed-off-by: Evgeny Boger <[email protected]>
---
drivers/net/ethernet/allwinner/sun4i-emac.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
index 5ed80d9a6b9f..c0ae06dd922c 100644
--- a/drivers/net/ethernet/allwinner/sun4i-emac.c
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
@@ -28,6 +28,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
+#include <linux/reset.h>
#include <linux/soc/sunxi/sunxi_sram.h>
#include "sun4i-emac.h"
@@ -85,6 +86,7 @@ struct emac_board_info {
unsigned int link;
unsigned int speed;
unsigned int duplex;
+ struct reset_control *reset;
phy_interface_t phy_interface;
};
@@ -791,6 +793,7 @@ static int emac_probe(struct platform_device *pdev)
struct net_device *ndev;
int ret = 0;
const char *mac_addr;
+ struct reset_control *reset;
ndev = alloc_etherdev(sizeof(struct emac_board_info));
if (!ndev) {
@@ -852,6 +855,19 @@ static int emac_probe(struct platform_device *pdev)
goto out_release_sram;
}
+ reset = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(reset)) {
+ dev_err(&pdev->dev, "unable to request reset\n");
+ ret = -ENODEV;
+ goto out_release_sram;
+ }
+ db->reset = reset;
+ ret = reset_control_deassert(db->reset);
+ if (ret) {
+ dev_err(&pdev->dev, "could not deassert EMAC reset\n");
+ goto out_release_sram;
+ }
+
/* Read MAC-address from DT */
mac_addr = of_get_mac_address(np);
if (!IS_ERR(mac_addr))
@@ -881,7 +897,7 @@ static int emac_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev, "Registering netdev failed!\n");
ret = -ENODEV;
- goto out_release_sram;
+ goto out_assert_reset;
}
dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
@@ -889,6 +905,8 @@ static int emac_probe(struct platform_device *pdev)
return 0;
+out_assert_reset:
+ reset_control_assert(db->reset);
out_release_sram:
sunxi_sram_release(&pdev->dev);
out_clk_disable_unprepare:
@@ -913,6 +931,7 @@ static int emac_remove(struct platform_device *pdev)
unregister_netdev(ndev);
sunxi_sram_release(&pdev->dev);
clk_disable_unprepare(db->clk);
+ reset_control_assert(db->reset);
irq_dispose_mapping(ndev->irq);
iounmap(db->membase);
free_netdev(ndev);
--
2.17.1
R40 (aka V40, A40i, T3) has two different Ethernet IP
called EMAC and GMAC.
EMAC only support 10/100 Mbit in MII mode,
while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII).
In contrast to A10/A20 where GMAC and EMAC share the same pins
making EMAC somewhat pointless, on R40 EMAC can be routed to port H.
Both EMAC (on port H) and GMAC (on port A)
can be then enabled at the same time, allowing for two ethernet ports.
Signed-off-by: Evgeny Boger <[email protected]>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 53 ++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5ad3b9efd12..c102c1510012 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -217,6 +217,20 @@
#size-cells = <1>;
ranges;
+ sram_a: sram@0 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0xc000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00000000 0xc000>;
+
+ emac_sram: sram-section@8000 {
+ compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "okay";
+ };
+ };
+
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
@@ -541,6 +555,24 @@
drive-strength = <40>;
};
+ emac_ph_pins: emac-ph-pins {
+ pins = "PH8", "PH9", "PH10", "PH11",
+ "PH14", "PH15", "PH16", "PH17",
+ "PH18","PH19", "PH20", "PH21",
+ "PH22", "PH23", "PH24", "PH25",
+ "PH26", "PH27";
+ function = "emac";
+ };
+
+ emac_pa_pins: emac-pa-pins {
+ pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ function = "emac";
+ };
+
i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
@@ -885,6 +917,27 @@
};
};
+ emac: ethernet@1c0b000 {
+ syscon = <&ccu>;
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EMAC>;
+ resets = <&ccu RST_BUS_EMAC>;
+ allwinner,sram = <&emac_sram 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_ph_pins>;
+ status = "disabled";
+ };
+
+ emac_mdio: mdio@1c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-r40-mbus";
reg = <0x01c62000 0x1000>;
--
2.17.1
Hi,
On Sun, Mar 07, 2021 at 06:13:51AM +0300, Evgeny Boger wrote:
> R40 (aka V40/A40i/T3) and A10/A20 share the same EMAC IP.
> However, on R40 the EMAC is gated by default.
>
> Signed-off-by: Evgeny Boger <[email protected]>
On which device was it tested?
> ---
> drivers/net/ethernet/allwinner/sun4i-emac.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
> index 5ed80d9a6b9f..c0ae06dd922c 100644
> --- a/drivers/net/ethernet/allwinner/sun4i-emac.c
> +++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
> @@ -28,6 +28,7 @@
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/phy.h>
> +#include <linux/reset.h>
> #include <linux/soc/sunxi/sunxi_sram.h>
>
> #include "sun4i-emac.h"
> @@ -85,6 +86,7 @@ struct emac_board_info {
> unsigned int link;
> unsigned int speed;
> unsigned int duplex;
> + struct reset_control *reset;
You should align this with the rest of the other fields
>
> phy_interface_t phy_interface;
> };
> @@ -791,6 +793,7 @@ static int emac_probe(struct platform_device *pdev)
> struct net_device *ndev;
> int ret = 0;
> const char *mac_addr;
> + struct reset_control *reset;
>
> ndev = alloc_etherdev(sizeof(struct emac_board_info));
> if (!ndev) {
> @@ -852,6 +855,19 @@ static int emac_probe(struct platform_device *pdev)
> goto out_release_sram;
> }
>
> + reset = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(reset)) {
> + dev_err(&pdev->dev, "unable to request reset\n");
> + ret = -ENODEV;
> + goto out_release_sram;
> + }
Judging from your commit log, it's not really optional for the R40. The
way we usually deal with this is to have a structure associated with a
new compatible and have a flag tell if that compatible requires a reset
line or not.
The dt binding should also be amended to allow the reset property
> + db->reset = reset;
> + ret = reset_control_deassert(db->reset);
> + if (ret) {
> + dev_err(&pdev->dev, "could not deassert EMAC reset\n");
> + goto out_release_sram;
> + }
> +
The programming guidelines in the datasheet ask that the reset line must
be deasserted before the clock in enabled.
Maxime
Hi,
On Sun, Mar 07, 2021 at 06:13:53AM +0300, Evgeny Boger wrote:
> R40 (aka V40, A40i, T3) has two different Ethernet IP
> called EMAC and GMAC.
> EMAC only support 10/100 Mbit in MII mode,
> while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII).
>
> In contrast to A10/A20 where GMAC and EMAC share the same pins
> making EMAC somewhat pointless, on R40 EMAC can be routed to port H.
> Both EMAC (on port H) and GMAC (on port A)
> can be then enabled at the same time, allowing for two ethernet ports.
>
> Signed-off-by: Evgeny Boger <[email protected]>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 53 ++++++++++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index d5ad3b9efd12..c102c1510012 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -217,6 +217,20 @@
> #size-cells = <1>;
> ranges;
>
> + sram_a: sram@0 {
> + compatible = "mmio-sram";
> + reg = <0x00000000 0xc000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00000000 0xc000>;
> +
> + emac_sram: sram-section@8000 {
> + compatible = "allwinner,sun4i-a10-sram-a3-a4";
> + reg = <0x8000 0x4000>;
> + status = "okay";
> + };
> + };
> +
> sram_c: sram@1d00000 {
> compatible = "mmio-sram";
> reg = <0x01d00000 0xd0000>;
> @@ -541,6 +555,24 @@
> drive-strength = <40>;
> };
>
> + emac_ph_pins: emac-ph-pins {
> + pins = "PH8", "PH9", "PH10", "PH11",
> + "PH14", "PH15", "PH16", "PH17",
> + "PH18","PH19", "PH20", "PH21",
> + "PH22", "PH23", "PH24", "PH25",
> + "PH26", "PH27";
> + function = "emac";
> + };
> +
> + emac_pa_pins: emac-pa-pins {
> + pins = "PA0", "PA1", "PA2",
> + "PA3", "PA4", "PA5", "PA6",
> + "PA7", "PA8", "PA9", "PA10",
> + "PA11", "PA12", "PA13", "PA14",
> + "PA15", "PA16";
> + function = "emac";
> + };
> +
These nodes should be order alphabetically
> i2c0_pins: i2c0-pins {
> pins = "PB0", "PB1";
> function = "i2c0";
> @@ -885,6 +917,27 @@
> };
> };
>
> + emac: ethernet@1c0b000 {
> + syscon = <&ccu>;
Why is the syscon needed? You weren't using it in the driver
> + compatible = "allwinner,sun4i-a10-emac";
> + reg = <0x01c0b000 0x1000>;
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_EMAC>;
> + resets = <&ccu RST_BUS_EMAC>;
> + allwinner,sram = <&emac_sram 1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_ph_pins>;
If there's several options, we really can't enforce a default here, it
should be in the board DTS.
Maxime
Hi, thank you for your review!
3/8/21 4:36 PM, Maxime Ripard пишет:
> Hi,
>
> On Sun, Mar 07, 2021 at 06:13:51AM +0300, Evgeny Boger wrote:
>> R40 (aka V40/A40i/T3) and A10/A20 share the same EMAC IP.
>> However, on R40 the EMAC is gated by default.
>>
>> Signed-off-by: Evgeny Boger <[email protected]>
> On which device was it tested?
It's custom-made Allwinner A40i device with two IP101GRI PHYs in MII mode.
>> ---
>> drivers/net/ethernet/allwinner/sun4i-emac.c | 21 ++++++++++++++++++++-
>> 1 file changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
>> index 5ed80d9a6b9f..c0ae06dd922c 100644
>> --- a/drivers/net/ethernet/allwinner/sun4i-emac.c
>> +++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
>> @@ -28,6 +28,7 @@
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/phy.h>
>> +#include <linux/reset.h>
>> #include <linux/soc/sunxi/sunxi_sram.h>
>>
>> #include "sun4i-emac.h"
>> @@ -85,6 +86,7 @@ struct emac_board_info {
>> unsigned int link;
>> unsigned int speed;
>> unsigned int duplex;
>> + struct reset_control *reset;
> You should align this with the rest of the other fields
>
>>
>> phy_interface_t phy_interface;
>> };
>> @@ -791,6 +793,7 @@ static int emac_probe(struct platform_device *pdev)
>> struct net_device *ndev;
>> int ret = 0;
>> const char *mac_addr;
>> + struct reset_control *reset;
>>
>> ndev = alloc_etherdev(sizeof(struct emac_board_info));
>> if (!ndev) {
>> @@ -852,6 +855,19 @@ static int emac_probe(struct platform_device *pdev)
>> goto out_release_sram;
>> }
>>
>> + reset = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
>> + if (IS_ERR(reset)) {
>> + dev_err(&pdev->dev, "unable to request reset\n");
>> + ret = -ENODEV;
>> + goto out_release_sram;
>> + }
> Judging from your commit log, it's not really optional for the R40. The
> way we usually deal with this is to have a structure associated with a
> new compatible and have a flag tell if that compatible requires a reset
> line or not.
>
> The dt binding should also be amended to allow the reset property
>
got it
>> + db->reset = reset;
>> + ret = reset_control_deassert(db->reset);
>> + if (ret) {
>> + dev_err(&pdev->dev, "could not deassert EMAC reset\n");
>> + goto out_release_sram;
>> + }
>> +
> The programming guidelines in the datasheet ask that the reset line must
> be deasserted before the clock in enabled.
right, found it at section 3.3.2.6, thanks
>
> Maxime