From: Konstantin Porotchkin <[email protected]>
This series of patches adds a new PHY driver for supporting CP110 UTMI
PHY in Linux. Currently the functionality of USB ports connected to
this PHY depends on boot loader setup.
The new driver eliminates kernel configuration dependency from the boot
loader.
v3:
- rebase on top of Linux 5.12-rc2
- convert Armada 3700 UTMI PHY DT binding document to YAML schema
- create a separate DT binding for Armada CP11x UTMI PHY in YAML format
- change UTMI PHY port node names from "phy" to "usb-phy"
v2:
- extend the comment about reference clock
- fix driver probe function, add some prints
- move to usage of dr_mode from connected USB controller instead of
dedicated device tree property
Konstantin Porotchkin (5):
drivers: phy: add support for Armada CP110 UTMI PHY
dt-bindings: phy: convert phy-mvebu-utmi to YAML schema
devicetree/bindings: add support for CP110 UTMI PHY
arch/arm64: dts: add support for Marvell CP110 UTMI PHY
arch/arm64: dts: enable CP110 UTMI PHY usage
.../phy/marvell,armada-3700-utmi-phy.yaml | 57 +++
.../phy/marvell,armada-cp110-utmi-phy.yaml | 109 +++++
.../bindings/phy/phy-mvebu-utmi.txt | 38 --
.../arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
.../arm64/boot/dts/marvell/armada-8040-db.dts | 21 +-
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +-
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +
arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +-
arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +-
arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 +-
drivers/phy/marvell/Kconfig | 8 +
drivers/phy/marvell/Makefile | 1 +
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 ++++++++++++++++++
13 files changed, 650 insertions(+), 52 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add support for Marvell CP110 UTMI PHY driver allowing the USB2
port configuration independently from the boot loader setup.
The CP110/CP115 dies have 2 UTMI PHYs that could be connected
to two USB host controllers or to single USB device controller.
Since there is only one USB device controller on die, only one
of the UTMI PHYs could work in USB device mode.
The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of
this driver.
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
drivers/phy/marvell/Kconfig | 8 +
drivers/phy/marvell/Makefile | 1 +
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 ++++++++++++++++++++
3 files changed, 393 insertions(+)
create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
index 6c96f2bf5266..9208839019bd 100644
--- a/drivers/phy/marvell/Kconfig
+++ b/drivers/phy/marvell/Kconfig
@@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY
lanes can be used by various controllers (Ethernet, sata, usb,
PCIe...).
+config PHY_MVEBU_CP110_UTMI
+ tristate "Marvell CP110 UTMI driver"
+ depends on ARCH_MVEBU || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support Marvell CP110 UTMI PHY driver.
+
config PHY_MVEBU_SATA
def_bool y
depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD
diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
index 7f296ef02829..90862c4daa26 100644
--- a/drivers/phy/marvell/Makefile
+++ b/drivers/phy/marvell/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o
obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
+obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
new file mode 100644
index 000000000000..08d178a4dc13
--- /dev/null
+++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Marvell
+ *
+ * Authors:
+ * Konstantin Porotchkin <[email protected]>
+ *
+ * Marvell CP110 UTMI PHY driver
+ */
+
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/usb/of.h>
+#include <linux/usb/otg.h>
+
+#define UTMI_PHY_PORTS 2
+
+/* CP110 UTMI register macro definetions */
+#define SYSCON_USB_CFG_REG 0x420
+#define USB_CFG_DEVICE_EN_MASK BIT(0)
+#define USB_CFG_DEVICE_MUX_OFFSET 1
+#define USB_CFG_DEVICE_MUX_MASK BIT(1)
+#define USB_CFG_PLL_MASK BIT(25)
+
+#define SYSCON_UTMI_CFG_REG(id) (0x440 + (id) * 4)
+#define UTMI_PHY_CFG_PU_MASK BIT(5)
+
+#define UTMI_PLL_CTRL_REG 0x0
+#define PLL_REFDIV_OFFSET 0
+#define PLL_REFDIV_MASK GENMASK(6, 0)
+#define PLL_REFDIV_VAL 0x5
+#define PLL_FBDIV_OFFSET 16
+#define PLL_FBDIV_MASK GENMASK(24, 16)
+#define PLL_FBDIV_VAL 0x60
+#define PLL_SEL_LPFR_MASK GENMASK(29, 28)
+#define PLL_RDY BIT(31)
+#define UTMI_CAL_CTRL_REG 0x8
+#define IMPCAL_VTH_OFFSET 8
+#define IMPCAL_VTH_MASK GENMASK(10, 8)
+#define IMPCAL_VTH_VAL 0x7
+#define IMPCAL_DONE BIT(23)
+#define PLLCAL_DONE BIT(31)
+#define UTMI_TX_CH_CTRL_REG 0xC
+#define DRV_EN_LS_OFFSET 12
+#define DRV_EN_LS_MASK GENMASK(15, 12)
+#define IMP_SEL_LS_OFFSET 16
+#define IMP_SEL_LS_MASK GENMASK(19, 16)
+#define TX_AMP_OFFSET 20
+#define TX_AMP_MASK GENMASK(22, 20)
+#define TX_AMP_VAL 0x4
+#define UTMI_RX_CH_CTRL0_REG 0x14
+#define SQ_DET_EN BIT(15)
+#define SQ_ANA_DTC_SEL BIT(28)
+#define UTMI_RX_CH_CTRL1_REG 0x18
+#define SQ_AMP_CAL_OFFSET 0
+#define SQ_AMP_CAL_MASK GENMASK(2, 0)
+#define SQ_AMP_CAL_VAL 1
+#define SQ_AMP_CAL_EN BIT(3)
+#define UTMI_CTRL_STATUS0_REG 0x24
+#define SUSPENDM BIT(22)
+#define TEST_SEL BIT(25)
+#define UTMI_CHGDTC_CTRL_REG 0x38
+#define VDAT_OFFSET 8
+#define VDAT_MASK GENMASK(9, 8)
+#define VDAT_VAL 1
+#define VSRC_OFFSET 10
+#define VSRC_MASK GENMASK(11, 10)
+#define VSRC_VAL 1
+
+#define PLL_LOCK_DELAY_US 10000
+#define PLL_LOCK_TIMEOUT_US 1000000
+
+#define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000)
+
+/**
+ * struct mvebu_cp110_utmi - PHY driver data
+ *
+ * @regs: PHY registers
+ * @syscom: Regmap with system controller registers
+ * @dev: device driver handle
+ * @caps: PHY capabilities
+ */
+struct mvebu_cp110_utmi {
+ void __iomem *regs;
+ struct regmap *syscon;
+ struct device *dev;
+ const struct phy_ops *ops;
+};
+
+/**
+ * struct mvebu_cp110_utmi_port - PHY port data
+ *
+ * @priv: PHY driver data
+ * @id: PHY port ID
+ * @dr_mode: PHY connection: USB_DR_MODE_HOST or USB_DR_MODE_PERIPHERAL
+ */
+struct mvebu_cp110_utmi_port {
+ struct mvebu_cp110_utmi *priv;
+ u32 id;
+ enum usb_dr_mode dr_mode;
+};
+
+static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port *port)
+{
+ u32 reg;
+
+ /*
+ * Setup PLL.
+ * The reference clock is the frequency of quartz resonator
+ * connected to pins REFCLK_XIN and REFCLK_XOUT of the SoC.
+ * Register init values are matching the 40MHz default clock.
+ * The crystal used for all platform boards is now 25MHz.
+ * See the functional specification for details.
+ */
+ reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG);
+ reg &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK | PLL_SEL_LPFR_MASK);
+ reg |= (PLL_REFDIV_VAL << PLL_REFDIV_OFFSET) |
+ (PLL_FBDIV_VAL << PLL_FBDIV_OFFSET);
+ writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG);
+
+ /* Impedance Calibration Threshold Setting */
+ reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG);
+ reg &= ~IMPCAL_VTH_MASK;
+ reg |= IMPCAL_VTH_VAL << IMPCAL_VTH_OFFSET;
+ writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG);
+
+ /* Set LS TX driver strength coarse control */
+ reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
+ reg &= ~TX_AMP_MASK;
+ reg |= TX_AMP_VAL << TX_AMP_OFFSET;
+ writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
+
+ /* Disable SQ and enable analog squelch detect */
+ reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
+ reg &= ~SQ_DET_EN;
+ reg |= SQ_ANA_DTC_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
+
+ /*
+ * Set External squelch calibration number and
+ * enable the External squelch calibration
+ */
+ reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
+ reg &= ~SQ_AMP_CAL_MASK;
+ reg |= (SQ_AMP_CAL_VAL << SQ_AMP_CAL_OFFSET) | SQ_AMP_CAL_EN;
+ writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
+
+ /*
+ * Set Control VDAT Reference Voltage - 0.325V and
+ * Control VSRC Reference Voltage - 0.6V
+ */
+ reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
+ reg &= ~(VDAT_MASK | VSRC_MASK);
+ reg |= (VDAT_VAL << VDAT_OFFSET) | (VSRC_VAL << VSRC_OFFSET);
+ writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
+}
+
+static int mvebu_cp110_utmi_phy_power_off(struct phy *phy)
+{
+ struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
+ struct mvebu_cp110_utmi *utmi = port->priv;
+ int i;
+
+ /* Power down UTMI PHY port */
+ regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
+ UTMI_PHY_CFG_PU_MASK);
+
+ for (i = 0; i < UTMI_PHY_PORTS; i++) {
+ int test = regmap_test_bits(utmi->syscon,
+ SYSCON_UTMI_CFG_REG(i),
+ UTMI_PHY_CFG_PU_MASK);
+ /* skip PLL shutdown if there are active UTMI PHY ports */
+ if (test != 0)
+ return 0;
+ }
+
+ /* PLL Power down if all UTMI PHYs are down */
+ regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
+
+ return 0;
+}
+
+static int mvebu_cp110_utmi_phy_power_on(struct phy *phy)
+{
+ struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
+ struct mvebu_cp110_utmi *utmi = port->priv;
+ struct device *dev = &phy->dev;
+ int ret;
+ u32 reg;
+
+ /* It is necessary to power off UTMI before configuration */
+ ret = mvebu_cp110_utmi_phy_power_off(phy);
+ if (ret) {
+ dev_err(dev, "UTMI power OFF before power ON failed\n");
+ return ret;
+ }
+
+ /*
+ * If UTMI port is connected to USB Device controller,
+ * configure the USB MUX prior to UTMI PHY initialization.
+ * The single USB device controller can be connected
+ * to UTMI0 or to UTMI1 PHY port, but not to both.
+ */
+ if (port->dr_mode == USB_DR_MODE_PERIPHERAL) {
+ regmap_update_bits(utmi->syscon, SYSCON_USB_CFG_REG,
+ USB_CFG_DEVICE_EN_MASK | USB_CFG_DEVICE_MUX_MASK,
+ USB_CFG_DEVICE_EN_MASK |
+ (port->id << USB_CFG_DEVICE_MUX_OFFSET));
+ }
+
+ /* Set Test suspendm mode and enable Test UTMI select */
+ reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+ reg |= SUSPENDM | TEST_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+
+ /* Wait for UTMI power down */
+ mdelay(1);
+
+ /* PHY port setup first */
+ mvebu_cp110_utmi_port_setup(port);
+
+ /* Power UP UTMI PHY */
+ regmap_set_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
+ UTMI_PHY_CFG_PU_MASK);
+
+ /* Disable Test UTMI select */
+ reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+ reg &= ~TEST_SEL;
+ writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
+
+ /* Wait for impedance calibration */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
+ reg & IMPCAL_DONE,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "Failed to end UTMI impedance calibration\n");
+ return ret;
+ }
+
+ /* Wait for PLL calibration */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
+ reg & PLLCAL_DONE,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "Failed to end UTMI PLL calibration\n");
+ return ret;
+ }
+
+ /* Wait for PLL ready */
+ ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg,
+ reg & PLL_RDY,
+ PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
+ if (ret) {
+ dev_err(dev, "PLL is not ready\n");
+ return ret;
+ }
+
+ /* PLL Power up */
+ regmap_set_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
+
+ return 0;
+}
+
+static const struct phy_ops mvebu_cp110_utmi_phy_ops = {
+ .power_on = mvebu_cp110_utmi_phy_power_on,
+ .power_off = mvebu_cp110_utmi_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id mvebu_cp110_utmi_of_match[] = {
+ { .compatible = "marvell,cp110-utmi-phy" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mvebu_cp110_utmi_of_match);
+
+static int mvebu_cp110_utmi_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mvebu_cp110_utmi *utmi;
+ struct phy_provider *provider;
+ struct device_node *child;
+ u32 usb_devices = 0;
+
+ utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return -ENOMEM;
+
+ utmi->dev = dev;
+
+ /* Get system controller region */
+ utmi->syscon = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "marvell,system-controller");
+ if (IS_ERR(utmi->syscon)) {
+ dev_err(dev, "Missing UTMI system controller\n");
+ return PTR_ERR(utmi->syscon);
+ }
+
+ /* Get UTMI memory region */
+ utmi->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(utmi->regs))
+ return PTR_ERR(utmi->regs);
+
+ for_each_available_child_of_node(dev->of_node, child) {
+ struct mvebu_cp110_utmi_port *port;
+ struct phy *phy;
+ int ret;
+ u32 port_id;
+
+ ret = of_property_read_u32(child, "reg", &port_id);
+ if ((ret < 0) || (port_id >= UTMI_PHY_PORTS)) {
+ dev_err(dev,
+ "invalid 'reg' property on child %pOF\n",
+ child);
+ continue;
+ }
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ port->dr_mode = of_usb_get_dr_mode_by_phy(child, -1);
+ if ((port->dr_mode != USB_DR_MODE_HOST) &&
+ (port->dr_mode != USB_DR_MODE_PERIPHERAL)) {
+ dev_err(&pdev->dev,
+ "Missing dual role setting of the port%d, will use HOST mode\n",
+ port_id);
+ port->dr_mode = USB_DR_MODE_HOST;
+ }
+
+ if (port->dr_mode == USB_DR_MODE_PERIPHERAL) {
+ usb_devices++;
+ if (usb_devices > 1) {
+ dev_err(dev,
+ "Single USB device allowed! Port%d will use HOST mode\n",
+ port_id);
+ port->dr_mode = USB_DR_MODE_HOST;
+ }
+ }
+
+ /* Retrieve PHY capabilities */
+ utmi->ops = &mvebu_cp110_utmi_phy_ops;
+
+ /* Instantiate the PHY */
+ phy = devm_phy_create(dev, child, utmi->ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "Failed to create the UTMI PHY\n");
+ of_node_put(child);
+ return PTR_ERR(phy);
+ }
+
+ port->priv = utmi;
+ port->id = port_id;
+ phy_set_drvdata(phy, port);
+
+ /* Ensure the PHY is powered off */
+ mvebu_cp110_utmi_phy_power_off(phy);
+ }
+
+ dev_set_drvdata(dev, utmi);
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver mvebu_cp110_utmi_driver = {
+ .probe = mvebu_cp110_utmi_phy_probe,
+ .driver = {
+ .name = "mvebu-cp110-utmi-phy",
+ .of_match_table = mvebu_cp110_utmi_of_match,
+ },
+};
+module_platform_driver(mvebu_cp110_utmi_driver);
+
+MODULE_AUTHOR("Konstatin Porotchkin <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada CP110 UTMI PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add support for Marvell CP110 UTMI PHY in a common DTSI
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 64179a372ecf..49f9d2cd8619 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -285,6 +285,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x580000 0x2000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): usb-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): usb-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
The new file name is marvell,armada-3700-utmi-phy.yaml
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml | 57 ++++++++++++++++++++
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 38 -------------
2 files changed, 57 insertions(+), 38 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
diff --git a/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
new file mode 100644
index 000000000000..2437c3683326
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Marvell Armada UTMI/UTMI+ PHY
+
+maintainers:
+ - Miquel Raynal <[email protected]>
+
+description:
+ On Armada 3700, there are two USB controllers, one is compatible with
+ the USB2 and USB3 specifications and supports OTG. The other one is USB2
+ compliant and only supports host mode. Both of these controllers come with
+ a slightly different UTMI PHY.
+
+properties:
+ compatible:
+ enum:
+ - marvell,a3700-utmi-host-phy
+ - marvell,a3700-utmi-otg-phy
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ marvell,usb-misc-reg:
+ description:
+ Phandle on the "USB miscellaneous registers" shared region
+ covering registers related to both the host controller and
+ the PHY.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - marvell,usb-misc-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ usb2_utmi_host_phy: phy@5f000 {
+ compatible = "marvell,armada-3700-utmi-host-phy";
+ reg = <0x5f000 0x800>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb2_syscon: system-controller@5f800 {
+ compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
+ reg = <0x5f800 0x800>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
deleted file mode 100644
index aa99ceec73b0..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MVEBU A3700 UTMI PHY
---------------------
-
-USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
-* Armada 3700
-
-On Armada 3700, there are two USB controllers, one is compatible with the USB2
-and USB3 specifications and supports OTG. The other one is USB2 compliant and
-only supports host mode. Both of these controllers come with a slightly
-different UTMI PHY.
-
-Required Properties:
-
-- compatible: Should be one of:
- * "marvell,a3700-utmi-host-phy" for the PHY connected to
- the USB2 host-only controller.
- * "marvell,a3700-utmi-otg-phy" for the PHY connected to
- the USB3 and USB2 OTG capable controller.
-- reg: PHY IP register range.
-- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
- region covering registers related to both the host
- controller and the PHY.
-- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
-
-
-Example:
-
- usb2_utmi_host_phy: phy@5f000 {
- compatible = "marvell,armada-3700-utmi-host-phy";
- reg = <0x5f000 0x800>;
- marvell,usb-misc-reg = <&usb2_syscon>;
- #phy-cells = <0>;
- };
-
- usb2_syscon: system-controller@5f800 {
- compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
- reg = <0x5f800 0x800>;
- };
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add DTS binding for Marvell CP110 UTMI PHY
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml | 109 ++++++++++++++++++++
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
new file mode 100644
index 000000000000..30f3b5f32a95
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Marvell Armada CP110/CP115 UTMI PHY
+
+maintainers:
+ - Konstantin Porotchkin <[email protected]>
+
+description:
+ On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
+ Each of two exiting UTMI PHYs could be connected to either USB host or USB device
+ controller.
+ The USB device controller can only be connected to a single UTMI PHY port
+ 0.H----- USB HOST0
+ UTMI PHY0 --------/
+ 0.D-----0
+ \------ USB DEVICE
+ 1.D-----1
+ UTMI PHY1 --------\
+ 1.H----- USB HOST1
+
+properties:
+ compatible:
+ const: marvell,cp110-utmi-phy
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ marvell,system-controller:
+ description:
+ Phandle to the system controller node
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+#Required child nodes:
+
+patternProperties:
+ "^usb-phy@[0|1]$":
+ type: object
+ description:
+ Each UTMI PHY port must be represented as a sub-node.
+
+ properties:
+ reg:
+ description: phy port index.
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - marvell,system-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ cp0_utmi: utmi@580000 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x580000 0x2000>;
+ marvell,system-controller = <&cp0_syscon0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cp0_utmi0: usb-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ cp0_utmi1: usb-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ /* UTMI0 is connected to USB host controller (default mode) */
+ dr_mode = "host";
+ };
+
+ cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
+ /* UTMI1 is connected to USB device controller */
+ dr_mode = "peripheral";
+ };
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +++++++++----
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 21 ++++++++++++++++++--
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 19 ++++++++++++++++--
arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +++++++++--
arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +++++++--
arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 ++++++++--
6 files changed, 72 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..51f3e2907597 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -218,6 +218,10 @@
};
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_comphy1 {
cp0_usbh0_con: connector {
compatible = "usb-a-connector";
@@ -226,8 +230,9 @@
};
&cp0_usb3_0 {
- phys = <&cp0_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
+ phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -239,8 +244,9 @@
};
&cp0_usb3_1 {
- phys = <&cp0_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "cp0-usb3h1-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..e39e1efc95b6 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -154,8 +154,15 @@
};
/* CON9 on CP0 expansion */
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -168,8 +175,9 @@
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
- phys = <&cp0_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -306,14 +314,23 @@
};
};
+&cp1_utmi {
+ status = "okay";
+};
+
/* CON9 on CP1 expansion */
&cp1_usb3_0 {
usb-phy = <&cp1_usb3_0_phy>;
+ phys = <&cp1_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
/* CON10 on CP1 expansion */
&cp1_usb3_1 {
+ phys = <&cp1_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..adbfecc678b5 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -259,13 +259,23 @@
vqmmc-supply = <&v_3_3>;
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
/* J38? - USB2.0 only */
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
&cp0_usb3_1 {
/* J38? - USB2.0 only */
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -364,9 +374,14 @@
};
};
+&cp1_utmi {
+ status = "okay";
+};
+
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
- phys = <&cp1_comphy2 0>;
- phy-names = "cp1-usb3h0-comphy";
+ phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
+ phy-names = "cp1-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index 79020e6d2792..2c2af001619b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -392,14 +392,22 @@
};
};
+&cp0_utmi {
+ status = "okay";
+};
+
&cp0_usb3_0 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy0>;
- phy-names = "usb";
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
&cp0_usb3_1 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy1>;
- phy-names = "usb";
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..ba2d4e1da159 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -193,10 +193,15 @@
};
/* CON58 */
+&cp1_utmi {
+ status = "okay";
+};
+
&cp1_usb3_1 {
status = "okay";
usb-phy = <&cp1_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy3 1>;
- phy-names = "usb";
+ phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts
index 4ef0df3097ca..81fba024b22d 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dts
@@ -205,17 +205,24 @@
};
};
+&cp2_utmi {
+ status = "okay";
+};
+
&cp2_usb3_0 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy0>;
+ phys = <&cp2_utmi0>;
phy-names = "usb";
+ dr_mode = "host";
};
/* SLM-1521-V2, CON11 */
&cp2_usb3_1 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy1>;
- phy-names = "usb";
/* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy3 1>;
+ phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode = "host";
};
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
Add support for Marvell CP110 UTMI PHY in a CP11x DTSI
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 64179a372ecf..49f9d2cd8619 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -285,6 +285,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x580000 0x2000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): usb-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): usb-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
This one sent by mistake, please ignore it.
There is another v3 4/5 that has a correct name.
Sorry for the mess.
Kosta
> -----Original Message-----
> From: [email protected] <[email protected]>
> Sent: Sunday, March 7, 2021 18:34
> To: [email protected]; [email protected]; linux-
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; Nadav
> Haklai <[email protected]>; Stefan Chulski <[email protected]>; Ben
> Peled <[email protected]>; Kostya Porotchkin <[email protected]>
> Subject: [PATCH v3 4/5] arch/arm64: dts: add support for Marvell CP110 UTMI
> driver
>
> From: Konstantin Porotchkin <[email protected]>
>
> Add support for Marvell CP110 UTMI PHY in a common DTSI
>
> Signed-off-by: Konstantin Porotchkin <[email protected]>
> ---
> arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> index 64179a372ecf..49f9d2cd8619 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> @@ -285,6 +285,25 @@
> };
> };
>
> + CP11X_LABEL(utmi): utmi@580000 {
> + compatible = "marvell,cp110-utmi-phy";
> + reg = <0x580000 0x2000>;
> + marvell,system-controller =
> <&CP11X_LABEL(syscon0)>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + CP11X_LABEL(utmi0): usb-phy@0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
> + CP11X_LABEL(utmi1): usb-phy@1 {
> + reg = <1>;
> + #phy-cells = <0>;
> + };
> + };
> +
> CP11X_LABEL(usb3_0): usb@500000 {
> compatible = "marvell,armada-8k-xhci",
> "generic-xhci";
> --
> 2.17.1
On Sun, 07 Mar 2021 18:33:39 +0200, [email protected] wrote:
> From: Konstantin Porotchkin <[email protected]>
>
> The new file name is marvell,armada-3700-utmi-phy.yaml
>
> Signed-off-by: Konstantin Porotchkin <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml | 57 ++++++++++++++++++++
> Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 38 -------------
> 2 files changed, 57 insertions(+), 38 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
>
Reviewed-by: Rob Herring <[email protected]>
On Sun, 07 Mar 2021 18:33:40 +0200, [email protected] wrote:
> From: Konstantin Porotchkin <[email protected]>
>
> Add DTS binding for Marvell CP110 UTMI PHY
>
> Signed-off-by: Konstantin Porotchkin <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml | 109 ++++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On 07-03-21, 18:33, [email protected] wrote:
> From: Konstantin Porotchkin <[email protected]>
>
> This series of patches adds a new PHY driver for supporting CP110 UTMI
> PHY in Linux. Currently the functionality of USB ports connected to
> this PHY depends on boot loader setup.
> The new driver eliminates kernel configuration dependency from the boot
> loader.
Applied 1-3, thanks
--
~Vinod
Hi Kosta,
> From: Konstantin Porotchkin <[email protected]>
>
> This series of patches adds a new PHY driver for supporting CP110 UTMI
> PHY in Linux. Currently the functionality of USB ports connected to
> this PHY depends on boot loader setup.
> The new driver eliminates kernel configuration dependency from the boot
> loader.
>
> v3:
> - rebase on top of Linux 5.12-rc2
> - convert Armada 3700 UTMI PHY DT binding document to YAML schema
> - create a separate DT binding for Armada CP11x UTMI PHY in YAML format
> - change UTMI PHY port node names from "phy" to "usb-phy"
>
> v2:
> - extend the comment about reference clock
> - fix driver probe function, add some prints
> - move to usage of dr_mode from connected USB controller instead of
> dedicated device tree property
>
> Konstantin Porotchkin (5):
> drivers: phy: add support for Armada CP110 UTMI PHY
> dt-bindings: phy: convert phy-mvebu-utmi to YAML schema
> devicetree/bindings: add support for CP110 UTMI PHY
> arch/arm64: dts: add support for Marvell CP110 UTMI PHY
> arch/arm64: dts: enable CP110 UTMI PHY usage
Patch 4 and 5 applied on mvebu/dt64.
I've just modified the title to align with the other commits in
arch/arm64/boot/dts/marvell. They now begin by "arm64: dts: marvell:".
Thanks,
Gregory
>
> .../phy/marvell,armada-3700-utmi-phy.yaml | 57 +++
> .../phy/marvell,armada-cp110-utmi-phy.yaml | 109 +++++
> .../bindings/phy/phy-mvebu-utmi.txt | 38 --
> .../arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
> .../arm64/boot/dts/marvell/armada-8040-db.dts | 21 +-
> .../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +-
> arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +
> arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +-
> arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +-
> arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 +-
> drivers/phy/marvell/Kconfig | 8 +
> drivers/phy/marvell/Makefile | 1 +
> drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 ++++++++++++++++++
> 13 files changed, 650 insertions(+), 52 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
> create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c
>
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com