LinuxLists.cc - [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode

2021-03-11 01:23:33

Subject: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode

A recent change to MIPS ralink reset logic made it so mt7530 actually
resets the switch on platforms such as mt7621 (where bit 2 is the reset
line for the switch). That exposed an issue where the switch would not
function properly in TRGMII mode after a reset.

Reconfigure core clock in TRGMII mode to fix the issue.

Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.

Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <[email protected]>
---
drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
1 file changed, 25 insertions(+), 27 deletions(-)

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index f06f5fa2f898..9871d7cff93a 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
TD_DM_DRVP(8) | TD_DM_DRVN(8));

/* Setup core clock for MT7530 */
- if (!trgint) {
- /* Disable MT7530 core clock */
- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
-
- /* Disable PLL, since phy_device has not yet been created
- * provided for phy_[read,write]_mmd_indirect is called, we
- * provide our own core_write_mmd_indirect to complete this
- * function.
- */
- core_write_mmd_indirect(priv,
- CORE_GSWPLL_GRP1,
- MDIO_MMD_VEND2,
- 0);
-
- /* Set core clock into 500Mhz */
- core_write(priv, CORE_GSWPLL_GRP2,
- RG_GSWPLL_POSDIV_500M(1) |
- RG_GSWPLL_FBKDIV_500M(25));
+ /* Disable MT7530 core clock */
+ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);

- /* Enable PLL */
- core_write(priv, CORE_GSWPLL_GRP1,
- RG_GSWPLL_EN_PRE |
- RG_GSWPLL_POSDIV_200M(2) |
- RG_GSWPLL_FBKDIV_200M(32));
-
- /* Enable MT7530 core clock */
- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
- }
+ /* Disable PLL, since phy_device has not yet been created
+ * provided for phy_[read,write]_mmd_indirect is called, we
+ * provide our own core_write_mmd_indirect to complete this
+ * function.
+ */
+ core_write_mmd_indirect(priv,
+ CORE_GSWPLL_GRP1,
+ MDIO_MMD_VEND2,
+ 0);
+
+ /* Set core clock into 500Mhz */
+ core_write(priv, CORE_GSWPLL_GRP2,
+ RG_GSWPLL_POSDIV_500M(1) |
+ RG_GSWPLL_FBKDIV_500M(25));
+
+ /* Enable PLL */
+ core_write(priv, CORE_GSWPLL_GRP1,
+ RG_GSWPLL_EN_PRE |
+ RG_GSWPLL_POSDIV_200M(2) |
+ RG_GSWPLL_FBKDIV_200M(32));
+
+ /* Enable MT7530 core clock */
+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);

/* Setup the MT7530 TRGMII Tx Clock */
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
--
2.30.2

2021-03-11 03:23:00

by Florian Fainelli

[permalink] [raw]

Subject: Re: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode

On 3/10/2021 5:21 PM, Ilya Lipnitskiy wrote:
> A recent change to MIPS ralink reset logic made it so mt7530 actually
> resets the switch on platforms such as mt7621 (where bit 2 is the reset
> line for the switch). That exposed an issue where the switch would not
> function properly in TRGMII mode after a reset.
>
> Reconfigure core clock in TRGMII mode to fix the issue.
>
> Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
>
> Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
> Signed-off-by: Ilya Lipnitskiy <[email protected]>

Reviewed-by: Florian Fainelli <[email protected]>
--
Florian

2021-03-12 11:44:17

by Ilya Lipnitskiy

[permalink] [raw]

Subject: [PATCH net,v2] net: dsa: mt7530: setup core clock even in TRGMII mode

2021-03-19 10:34:57

by René van Dorst

[permalink] [raw]

Subject: Re: [PATCH net,v2] net: dsa: mt7530: setup core clock even in TRGMII mode

Quoting Ilya Lipnitskiy <[email protected]>:

> A recent change to MIPS ralink reset logic made it so mt7530 actually
> resets the switch on platforms such as mt7621 (where bit 2 is the reset
> line for the switch). That exposed an issue where the switch would not
> function properly in TRGMII mode after a reset.
>
> Reconfigure core clock in TRGMII mode to fix the issue.
>
> Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
>
> Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
> Signed-off-by: Ilya Lipnitskiy <[email protected]>
> ---
> drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
> 1 file changed, 25 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index f06f5fa2f898..9871d7cff93a 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds,
> phy_interface_t interface)
> TD_DM_DRVP(8) | TD_DM_DRVN(8));
>
> /* Setup core clock for MT7530 */
> - if (!trgint) {
> - /* Disable MT7530 core clock */
> - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> -
> - /* Disable PLL, since phy_device has not yet been created
> - * provided for phy_[read,write]_mmd_indirect is called, we
> - * provide our own core_write_mmd_indirect to complete this
> - * function.
> - */
> - core_write_mmd_indirect(priv,
> - CORE_GSWPLL_GRP1,
> - MDIO_MMD_VEND2,
> - 0);
> -
> - /* Set core clock into 500Mhz */
> - core_write(priv, CORE_GSWPLL_GRP2,
> - RG_GSWPLL_POSDIV_500M(1) |
> - RG_GSWPLL_FBKDIV_500M(25));
> + /* Disable MT7530 core clock */
> + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
>
> - /* Enable PLL */
> - core_write(priv, CORE_GSWPLL_GRP1,
> - RG_GSWPLL_EN_PRE |
> - RG_GSWPLL_POSDIV_200M(2) |
> - RG_GSWPLL_FBKDIV_200M(32));
> -
> - /* Enable MT7530 core clock */
> - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> - }
> + /* Disable PLL, since phy_device has not yet been created
> + * provided for phy_[read,write]_mmd_indirect is called, we
> + * provide our own core_write_mmd_indirect to complete this
> + * function.
> + */
> + core_write_mmd_indirect(priv,
> + CORE_GSWPLL_GRP1,
> + MDIO_MMD_VEND2,
> + 0);
> +
> + /* Set core clock into 500Mhz */
> + core_write(priv, CORE_GSWPLL_GRP2,
> + RG_GSWPLL_POSDIV_500M(1) |
> + RG_GSWPLL_FBKDIV_500M(25));
> +
> + /* Enable PLL */
> + core_write(priv, CORE_GSWPLL_GRP1,
> + RG_GSWPLL_EN_PRE |
> + RG_GSWPLL_POSDIV_200M(2) |
> + RG_GSWPLL_FBKDIV_200M(32));
> +
> + /* Enable MT7530 core clock */
> + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
>
> /* Setup the MT7530 TRGMII Tx Clock */
> core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> --
> 2.30.2

Hi Ilya,

Thanks for fixing this issue.

I remember that Frank also had an issue with TRGMII on his MT7623 ARM board.
I never found why it did not work but this may be also fix his issue
on the MT7623 devices.

Added Frank to CC.

Tested on Ubiquiti ER-X-SFP (MT7621) with and without TRGMII mode enabled.

Tested-by: René van Dorst <[email protected]>

Greats,

René

2021-03-19 12:52:44

by Frank Wunderlich

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Subject: Aw: Re: [PATCH net,v2] net: dsa: mt7530: setup core clock even in TRGMII mode

Hi René,Ilya

> Gesendet: Freitag, 19. März 2021 um 11:25 Uhr
> Von: "René van Dorst" <[email protected]>
> Hi Ilya,
>
> Thanks for fixing this issue.
>
> I remember that Frank also had an issue with TRGMII on his MT7623 ARM board.
> I never found why it did not work but this may be also fix his issue
> on the MT7623 devices.
>
> Added Frank to CC.

thanks for pointing me here. my issue was after getting trgmii working with phylink-patches (5.3) that i only got only 940Mbit over the switch/gmac0 (using multiple clients to one iperf3-server), trgmii afair supports ~2.1 Gbit/s, so nearly twice bandwidth possible in theory. this maybe can clock-related

I'm not sure if it is the same issue ilya fixes here, but i try to test this on my bananapi-r2

regards Frank