2021-03-23 03:00:55

by xuyihang

Subject: [PATCH -next] x86: Fix intel cpu unsed variab le ‘l2’ warning

Fixes the following W=1 kernel build warning(s):
../arch/x86/kernel/cpu/intel.c: In function ‘init_intel’:
../arch/x86/kernel/cpu/intel.c:644:20: warning: variable ‘l2’ set but not used [-Wunused-but-set-variable]
unsigned int l1, l2;
^~

Compilation command(s):
make allmodconfig ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-
make W=1 arch/x86/kernel/cpu/intel.o ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-

According to Intel Software Developer's Manual Table 2-2 through Table 2-24 about MSRs:
X86_FEATURE_BTS which represents Branch Trace Storage Unavailable and X86_FEATURE_PEBS
represens Processor Event Based Sampling (PEBS) Unavailable, but on some platform these fields
maybe reserved or not available. For the function init_intel it self, only bit 11 and bit 12
are used for checking BTS and PEBS, and higher 32 bits are not used. So cast to void to
avoid warning.

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Xu Yihang <[email protected]>
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 63e381a46153..547ba6668eb3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -644,6 +644,7 @@ static void init_intel(struct cpuinfo_x86 *c)
unsigned int l1, l2;

rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+ (void) l2;
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l1 & (1<<12)))
--
2.17.1

2021-03-23 09:23:03

by Borislav Petkov

Subject: Re: [PATCH -next] x86: Fix intel cpu unsed variable ‘l2’ warning

On Tue, Mar 23, 2021 at 10:59:01AM +0800, Xu Yihang wrote:
> Fixes the following W=1 kernel build warning(s):
> ../arch/x86/kernel/cpu/intel.c: In function ‘init_intel’:
> ../arch/x86/kernel/cpu/intel.c:644:20: warning: variable ‘l2’ set but not used [-Wunused-but-set-variable]
> unsigned int l1, l2;
> ^~
>
> Compilation command(s):
> make allmodconfig ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-
> make W=1 arch/x86/kernel/cpu/intel.o ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-
>
> According to Intel Software Developer's Manual Table 2-2 through Table 2-24 about MSRs:
> X86_FEATURE_BTS which represents Branch Trace Storage Unavailable and X86_FEATURE_PEBS
> represens Processor Event Based Sampling (PEBS) Unavailable, but on some platform these fields
> maybe reserved or not available. For the function init_intel it self, only bit 11 and bit 12
> are used for checking BTS and PEBS, and higher 32 bits are not used. So cast to void to
> avoid warning.
>
> Reported-by: Hulk Robot <[email protected]>
> Signed-off-by: Xu Yihang <[email protected]>
> ---
> arch/x86/kernel/cpu/intel.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 63e381a46153..547ba6668eb3 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -644,6 +644,7 @@ static void init_intel(struct cpuinfo_x86 *c)
> unsigned int l1, l2;
>
> rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
> + (void) l2;
> if (!(l1 & (1<<11)))
> set_cpu_cap(c, X86_FEATURE_BTS);
> if (!(l1 & (1<<12)))
> --

Are you kidding me?

In what universe is this good idea?! Where have you seen other code like
that in the kernel and thought this makes sense?

I would strongly suggest you apply some brain matter and common sense
before sending patches like that and think real hard whether some
warnings need to be fixed at all cost and at all.

Because there's a reason these warnings are behind the W= switch.

Otherwise all your mail will land in /dev/null and you'll be purely
wasting your time.

Good luck!

--
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette