From: Hou Zhiqiang <[email protected]>
This patch series is to add PCIe power management support for NXP
Layerscape platforms.
Hou Zhiqiang (6):
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a optional property big-endian
arm64: dts: layerscape: Add big-endian property for PCIe nodes
dt-bindings: pci: layerscape-pci: Update the description of SCFG
property
arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
PCI: layerscape: Add power management support
.../bindings/pci/layerscape-pci.txt | 6 +-
.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +
drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.h | 1 +
6 files changed, 370 insertions(+), 97 deletions(-)
--
2.17.1
From: Hou Zhiqiang <[email protected]>
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common link-up check function.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
V5:
- No change
drivers/pci/controller/dwc/pci-layerscape.c | 140 ++------------------
1 file changed, 10 insertions(+), 130 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index 5b9c625df7b8..71911ca4c589 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -22,12 +22,6 @@
#include "pcie-designware.h"
-/* PEX1/2 Misc Ports Status Register */
-#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
-#define LTSSM_STATE_SHIFT 20
-#define LTSSM_STATE_MASK 0x3f
-#define LTSSM_PCIE_L0 0x11 /* L0 state */
-
/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
@@ -36,19 +30,12 @@
#define PCIE_IATU_NUM 6
struct ls_pcie_drvdata {
- u32 lut_offset;
- u32 ltssm_shift;
- u32 lut_dbg;
const struct dw_pcie_host_ops *ops;
- const struct dw_pcie_ops *dw_pcie_ops;
};
struct ls_pcie {
struct dw_pcie *pci;
- void __iomem *lut;
- struct regmap *scfg;
const struct ls_pcie_drvdata *drvdata;
- int index;
};
#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
@@ -83,38 +70,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
}
-static int ls1021_pcie_link_up(struct dw_pcie *pci)
-{
- u32 state;
- struct ls_pcie *pcie = to_ls_pcie(pci);
-
- if (!pcie->scfg)
- return 0;
-
- regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
- state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
-
- if (state < LTSSM_PCIE_L0)
- return 0;
-
- return 1;
-}
-
-static int ls_pcie_link_up(struct dw_pcie *pci)
-{
- struct ls_pcie *pcie = to_ls_pcie(pci);
- u32 state;
-
- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
- pcie->drvdata->ltssm_shift) &
- LTSSM_STATE_MASK;
-
- if (state < LTSSM_PCIE_L0)
- return 0;
-
- return 1;
-}
-
/* Forward error response of outbound non-posted requests */
static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
{
@@ -139,96 +94,24 @@ static int ls_pcie_host_init(struct pcie_port *pp)
return 0;
}
-static int ls1021_pcie_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct ls_pcie *pcie = to_ls_pcie(pci);
- struct device *dev = pci->dev;
- u32 index[2];
- int ret;
-
- pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
- "fsl,pcie-scfg");
- if (IS_ERR(pcie->scfg)) {
- ret = PTR_ERR(pcie->scfg);
- dev_err(dev, "No syscfg phandle specified\n");
- pcie->scfg = NULL;
- return ret;
- }
-
- if (of_property_read_u32_array(dev->of_node,
- "fsl,pcie-scfg", index, 2)) {
- pcie->scfg = NULL;
- return -EINVAL;
- }
- pcie->index = index[1];
-
- return ls_pcie_host_init(pp);
-}
-
-static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
- .host_init = ls1021_pcie_host_init,
-};
-
static const struct dw_pcie_host_ops ls_pcie_host_ops = {
.host_init = ls_pcie_host_init,
};
-static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
- .link_up = ls1021_pcie_link_up,
-};
-
-static const struct dw_pcie_ops dw_ls_pcie_ops = {
- .link_up = ls_pcie_link_up,
-};
-
-static const struct ls_pcie_drvdata ls1021_drvdata = {
- .ops = &ls1021_pcie_host_ops,
- .dw_pcie_ops = &dw_ls1021_pcie_ops,
-};
-
-static const struct ls_pcie_drvdata ls1043_drvdata = {
- .lut_offset = 0x10000,
- .ltssm_shift = 24,
- .lut_dbg = 0x7fc,
+static const struct ls_pcie_drvdata layerscape_drvdata = {
.ops = &ls_pcie_host_ops,
- .dw_pcie_ops = &dw_ls_pcie_ops,
-};
-
-static const struct ls_pcie_drvdata ls1046_drvdata = {
- .lut_offset = 0x80000,
- .ltssm_shift = 24,
- .lut_dbg = 0x407fc,
- .ops = &ls_pcie_host_ops,
- .dw_pcie_ops = &dw_ls_pcie_ops,
-};
-
-static const struct ls_pcie_drvdata ls2080_drvdata = {
- .lut_offset = 0x80000,
- .ltssm_shift = 0,
- .lut_dbg = 0x7fc,
- .ops = &ls_pcie_host_ops,
- .dw_pcie_ops = &dw_ls_pcie_ops,
-};
-
-static const struct ls_pcie_drvdata ls2088_drvdata = {
- .lut_offset = 0x80000,
- .ltssm_shift = 0,
- .lut_dbg = 0x407fc,
- .ops = &ls_pcie_host_ops,
- .dw_pcie_ops = &dw_ls_pcie_ops,
};
static const struct of_device_id ls_pcie_of_match[] = {
- { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
- { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
- { .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },
- { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
- { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
- { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
- { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
- { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
- { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
+ { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls1021a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls1043a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata },
+ { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata },
{ },
};
@@ -250,7 +133,6 @@ static int ls_pcie_probe(struct platform_device *pdev)
pcie->drvdata = of_device_get_match_data(dev);
pci->dev = dev;
- pci->ops = pcie->drvdata->dw_pcie_ops;
pci->pp.ops = pcie->drvdata->ops;
pcie->pci = pci;
@@ -260,8 +142,6 @@ static int ls_pcie_probe(struct platform_device *pdev)
if (IS_ERR(pci->dbi_base))
return PTR_ERR(pci->dbi_base);
- pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
-
if (!ls_pcie_is_bridge(pcie))
return -ENODEV;
--
2.17.1
From: Hou Zhiqiang <[email protected]>
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
V5:
- No change
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 46826752a691..704e9e249729 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -875,6 +875,7 @@
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
interrupt-names = "intr", "pme";
+ fsl,pcie-scfg = <&scfg 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -902,6 +903,7 @@
interrupts = <0 128 0x4>,
<0 127 0x4>;
interrupt-names = "intr", "pme";
+ fsl,pcie-scfg = <&scfg 1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -929,6 +931,7 @@
interrupts = <0 162 0x4>,
<0 161 0x4>;
interrupt-names = "intr", "pme";
+ fsl,pcie-scfg = <&scfg 2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
--
2.17.1
On Wed, Apr 7, 2021 at 9:13 AM Zhiqiang Hou <[email protected]> wrote:
>
> From: Hou Zhiqiang <[email protected]>
>
> This patch series is to add PCIe power management support for NXP
> Layerscape platforms.
>
> Hou Zhiqiang (6):
> PCI: layerscape: Change to use the DWC common link-up check function
> dt-bindings: pci: layerscape-pci: Add a optional property big-endian
> arm64: dts: layerscape: Add big-endian property for PCIe nodes
> dt-bindings: pci: layerscape-pci: Update the description of SCFG
> property
> arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
> PCI: layerscape: Add power management support
>
> .../bindings/pci/layerscape-pci.txt | 6 +-
> .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +
> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +
> drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++----
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 6 files changed, 370 insertions(+), 97 deletions(-)
Hi Bjorn,
I don't see any feedback on this version. Is there any chance that
the binding/driver changes can be picked up?
Regards,
Leo
On Thu, Nov 11, 2021 at 03:21:37PM -0600, Li Yang wrote:
> On Wed, Apr 7, 2021 at 9:13 AM Zhiqiang Hou <[email protected]> wrote:
> >
> > From: Hou Zhiqiang <[email protected]>
> >
> > This patch series is to add PCIe power management support for NXP
> > Layerscape platforms.
> >
> > Hou Zhiqiang (6):
> > PCI: layerscape: Change to use the DWC common link-up check function
> > dt-bindings: pci: layerscape-pci: Add a optional property big-endian
> > arm64: dts: layerscape: Add big-endian property for PCIe nodes
> > dt-bindings: pci: layerscape-pci: Update the description of SCFG
> > property
> > arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
> > PCI: layerscape: Add power management support
> >
> > .../bindings/pci/layerscape-pci.txt | 6 +-
> > .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
> > .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +
> > .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +
> > drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++----
> > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > 6 files changed, 370 insertions(+), 97 deletions(-)
>
> Hi Bjorn,
>
> I don't see any feedback on this version. Is there any chance that
> the binding/driver changes can be picked up?
Probably slipped through the cracks. We're in the middle of the v5.16
merge window right now. After v5.16-rc1 is tagged (probably Nov 14),
rebase your series on top of that, incorporate Rob's reviewed-by, and
repost it. Then Lorenzo will see it and take a look.
Bjorn
> -----Original Message-----
> From: Bjorn Helgaas <[email protected]>
> Sent: Thursday, November 11, 2021 3:45 PM
> To: Leo Li <[email protected]>
> Cc: Z.Q. Hou <[email protected]>; [email protected]; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <[email protected]>; lkml <[email protected]>;
> moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> [email protected]>; Lorenzo Pieralisi <[email protected]>;
> Rob Herring <[email protected]>; Bjorn Helgaas <[email protected]>;
> Shawn Guo <[email protected]>; [email protected];
> M.H. Lian <[email protected]>; Mingkai Hu <[email protected]>;
> Roy Zang <[email protected]>
> Subject: Re: [PATCHv5 0/6] PCI: layerscape: Add power management support
>
> On Thu, Nov 11, 2021 at 03:21:37PM -0600, Li Yang wrote:
> > On Wed, Apr 7, 2021 at 9:13 AM Zhiqiang Hou <[email protected]>
> wrote:
> > >
> > > From: Hou Zhiqiang <[email protected]>
> > >
> > > This patch series is to add PCIe power management support for NXP
> > > Layerscape platforms.
> > >
> > > Hou Zhiqiang (6):
> > > PCI: layerscape: Change to use the DWC common link-up check function
> > > dt-bindings: pci: layerscape-pci: Add a optional property big-endian
> > > arm64: dts: layerscape: Add big-endian property for PCIe nodes
> > > dt-bindings: pci: layerscape-pci: Update the description of SCFG
> > > property
> > > arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
> > > PCI: layerscape: Add power management support
> > >
> > > .../bindings/pci/layerscape-pci.txt | 6 +-
> > > .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
> > > .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +
> > > .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +
> > > drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++----
> > > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > > 6 files changed, 370 insertions(+), 97 deletions(-)
> >
> > Hi Bjorn,
> >
> > I don't see any feedback on this version. Is there any chance that
> > the binding/driver changes can be picked up?
>
> Probably slipped through the cracks. We're in the middle of the v5.16 merge
> window right now. After v5.16-rc1 is tagged (probably Nov 14), rebase your
> series on top of that, incorporate Rob's reviewed-by, and repost it. Then
> Lorenzo will see it and take a look.
Thanks Bjorn,
While we waiting for the repost and review for the driver change, the dt-binding
updates seems to be unrelated to the driver changes. So probably they can be
applied separately to make the dts changes mergeable?
Regards,
Leo