From: Mohammad Athari Bin Ismail <[email protected]>
This patch series to add setting for HW descriptor prefetch for DWMAC version 5.20 onwards. For Intel platform, enable the capability by default.
Mohammad Athari Bin Ismail (2):
net: stmmac: Add HW descriptor prefetch setting for DWMAC Core 5.20
onwards
stmmac: intel: Enable HW descriptor prefetch by default
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 ++++++++--
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++
include/linux/stmmac.h | 1 +
6 files changed, 17 insertions(+), 2 deletions(-)
--
2.17.1
From: Mohammad Athari Bin Ismail <[email protected]>
Enable HW descriptor prefetch by default by setting plat->dma_cfg->dche =
true in intel_mgbe_common_data(). Need to be noted that this capability
only be supported in DWMAC core version 5.20 onwards. In stmmac, there is
a checking to check the core version. If the core version is below 5.20,
this capability wouldn`t be configured.
Below is the iperf result comparison between HW descriptor prefetch
disabled(DCHE=0b) and enabled(DCHE=1b). Tested on Intel Elkhartlake
platform with DWMAC Core 5.20. Observed line rate performance
improvement with HW descriptor prefetch enabled.
DCHE = 0b
[ 5] local 169.254.1.162 port 42123 connected to 169.254.244.142 port 5201
[ ID] Interval Transfer Bitrate Total Datagrams
[ 5] 0.00-1.00 sec 96.7 MBytes 811 Mbits/sec 70050
[ 5] 1.00-2.00 sec 96.5 MBytes 809 Mbits/sec 69850
[ 5] 2.00-3.00 sec 96.3 MBytes 808 Mbits/sec 69720
[ 5] 3.00-4.00 sec 95.9 MBytes 804 Mbits/sec 69450
[ 5] 4.00-5.00 sec 96.0 MBytes 806 Mbits/sec 69530
[ 5] 5.00-6.00 sec 96.8 MBytes 812 Mbits/sec 70080
[ 5] 6.00-7.00 sec 96.9 MBytes 813 Mbits/sec 70140
[ 5] 7.00-8.00 sec 96.8 MBytes 812 Mbits/sec 70080
[ 5] 8.00-9.00 sec 97.0 MBytes 814 Mbits/sec 70230
[ 5] 9.00-10.00 sec 96.9 MBytes 813 Mbits/sec 70170
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Jitter Lost/Total Datagrams
[ 5] 0.00-10.00 sec 966 MBytes 810 Mbits/sec 0.000 ms 0/699300 (0%) sender
[ 5] 0.00-10.00 sec 966 MBytes 810 Mbits/sec 0.011 ms 0/699265 (0%) receiver
DCHE = 1b
[ 5] local 169.254.1.162 port 49740 connected to 169.254.244.142 port 5201
[ ID] Interval Transfer Bitrate Total Datagrams
[ 5] 0.00-1.00 sec 97.9 MBytes 821 Mbits/sec 70880
[ 5] 1.00-2.00 sec 98.1 MBytes 823 Mbits/sec 71060
[ 5] 2.00-3.00 sec 98.2 MBytes 824 Mbits/sec 71140
[ 5] 3.00-4.00 sec 98.2 MBytes 824 Mbits/sec 71090
[ 5] 4.00-5.00 sec 98.1 MBytes 823 Mbits/sec 71050
[ 5] 5.00-6.00 sec 98.1 MBytes 823 Mbits/sec 71040
[ 5] 6.00-7.00 sec 98.1 MBytes 823 Mbits/sec 71050
[ 5] 7.00-8.00 sec 98.2 MBytes 824 Mbits/sec 71140
[ 5] 8.00-9.00 sec 98.2 MBytes 824 Mbits/sec 71120
[ 5] 9.00-10.00 sec 98.3 MBytes 824 Mbits/sec 71150
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Jitter Lost/Total Datagrams
[ 5] 0.00-10.00 sec 981 MBytes 823 Mbits/sec 0.000 ms 0/710720 (0%) sender
[ 5] 0.00-10.00 sec 981 MBytes 823 Mbits/sec 0.041 ms 0/710650 (0%) receiver
Signed-off-by: Mohammad Athari Bin Ismail <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 4bd038acb1b9..80728a4c0e3f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -471,6 +471,7 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
plat->dma_cfg->fixed_burst = 0;
plat->dma_cfg->mixed_burst = 0;
plat->dma_cfg->aal = 0;
+ plat->dma_cfg->dche = true;
plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
GFP_KERNEL);
--
2.17.1
From: Mohammad Athari Bin Ismail <[email protected]>
DWMAC Core 5.20 onwards supports HW descriptor prefetching.
Additionally, it also depends on platform specific RTL configuration.
This capability could be enabled by setting DMA_Mode bit-19 (DCHE).
So, to enable this cability, platform must set plat->dma_cfg->dche = true
and the DWMAC core version must be 5.20 onwards. Else, this capability
wouldn`t be configured
Signed-off-by: Mohammad Athari Bin Ismail <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 ++++++++--
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++
include/linux/stmmac.h | 1 +
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index c54a56b732b3..619e3c0760d6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -33,6 +33,7 @@
#define DWMAC_CORE_4_10 0x41
#define DWMAC_CORE_5_00 0x50
#define DWMAC_CORE_5_10 0x51
+#define DWMAC_CORE_5_20 0x52
#define DWXGMAC_CORE_2_10 0x21
#define DWXLGMAC_CORE_2_00 0x20
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index cb17f6c35e54..a602d16b9e53 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -162,12 +162,18 @@ static void dwmac4_dma_init(void __iomem *ioaddr,
writel(value, ioaddr + DMA_SYS_BUS_MODE);
+ value = readl(ioaddr + DMA_BUS_MODE);
+
if (dma_cfg->multi_msi_en) {
- value = readl(ioaddr + DMA_BUS_MODE);
value &= ~DMA_BUS_MODE_INTM_MASK;
value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
- writel(value, ioaddr + DMA_BUS_MODE);
}
+
+ if (dma_cfg->dche)
+ value |= DMA_BUS_MODE_DCHE;
+
+ writel(value, ioaddr + DMA_BUS_MODE);
+
}
static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index 05481eb13ba6..9321879b599c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -25,6 +25,7 @@
#define DMA_TBS_CTRL 0x00001050
/* DMA Bus Mode bitmap */
+#define DMA_BUS_MODE_DCHE BIT(19)
#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
#define DMA_BUS_MODE_INTM_SHIFT 16
#define DMA_BUS_MODE_INTM_MODE1 0x1
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index d1ca07c846e6..372090e8ee6f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -6849,6 +6849,11 @@ int stmmac_dvr_probe(struct device *device,
if (ret)
goto error_hw_init;
+ /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
+ */
+ if (priv->synopsys_id < DWMAC_CORE_5_20)
+ priv->plat->dma_cfg->dche = false;
+
stmmac_check_ether_addr(priv);
ndev->netdev_ops = &stmmac_netdev_ops;
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 97edb31d6310..0db36360ef21 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -97,6 +97,7 @@ struct stmmac_dma_cfg {
bool aal;
bool eame;
bool multi_msi_en;
+ bool dche;
};
#define AXI_BLEN 7
--
2.17.1
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Thu, 22 Apr 2021 15:54:59 +0800 you wrote:
> From: Mohammad Athari Bin Ismail <[email protected]>
>
> This patch series to add setting for HW descriptor prefetch for DWMAC version 5.20 onwards. For Intel platform, enable the capability by default.
>
> Mohammad Athari Bin Ismail (2):
> net: stmmac: Add HW descriptor prefetch setting for DWMAC Core 5.20
> onwards
> stmmac: intel: Enable HW descriptor prefetch by default
>
> [...]
Here is the summary with links:
- [net-next,1/2] net: stmmac: Add HW descriptor prefetch setting for DWMAC Core 5.20 onwards
https://git.kernel.org/netdev/net-next/c/96874c619c20
- [net-next,2/2] stmmac: intel: Enable HW descriptor prefetch by default
https://git.kernel.org/netdev/net-next/c/676b7ec67d79
You are awesome, thank you!
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