2021-05-11 06:16:57

by Ben Chuang

Subject: [PATCH] mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay

Fine tune the value to 21us in order to improve read/write performance.

Signed-off-by: Ben Chuang <[email protected]>
---
drivers/mmc/host/sdhci-pci-gli.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 592d79082f58..73e01c3480a3 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -94,7 +94,7 @@

#define PCIE_GLI_9763E_CFG2 0x8A4
#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
-#define GLI_9763E_CFG2_L1DLY_MID 0x50
+#define GLI_9763E_CFG2_L1DLY_MID 0x54

#define PCIE_GLI_9763E_MMC_CTRL 0x960
#define GLI_9763E_HS400_SLOW BIT(3)
@@ -842,7 +842,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)

pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
value &= ~GLI_9763E_CFG2_L1DLY;
- /* set ASPM L1 entry delay to 20us */
+ /* set ASPM L1 entry delay to 21us */
value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);

--
2.31.1

2021-05-11 10:58:59

by Ulf Hansson

Subject: Re: [PATCH] mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay

On Tue, 11 May 2021 at 08:15, Ben Chuang <[email protected]> wrote:
>
> Fine tune the value to 21us in order to improve read/write performance.
>
> Signed-off-by: Ben Chuang <[email protected]>

Applied for next, thanks!

Kind regards
Uffe


> ---
> drivers/mmc/host/sdhci-pci-gli.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 592d79082f58..73e01c3480a3 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -94,7 +94,7 @@
>
> #define PCIE_GLI_9763E_CFG2 0x8A4
> #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
> -#define GLI_9763E_CFG2_L1DLY_MID 0x50
> +#define GLI_9763E_CFG2_L1DLY_MID 0x54
>
> #define PCIE_GLI_9763E_MMC_CTRL 0x960
> #define GLI_9763E_HS400_SLOW BIT(3)
> @@ -842,7 +842,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
>
> pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
> value &= ~GLI_9763E_CFG2_L1DLY;
> - /* set ASPM L1 entry delay to 20us */
> + /* set ASPM L1 entry delay to 21us */
> value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
> pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
>
> --
> 2.31.1
>