The RK3308 SoC features integrated USB controllers and PHYs. The USB
controller is compatible with the usual RK3066 USB controller, the phy is
in general compatible with the inno-usb2 phy structure but is not quite
the same as any of the phys supported yet.
This patchset adds USB support for the RK3308 SoC to both the RK3308 dtsi
and Rockchip inno-usb2 phy driver.
I've tested this patchset on a Rock Pi S, works flawlessly with HS, FS and
LS devices.
Cheers,
Tobias
Tobias Schramm (4):
Documentation: bindings: phy: add compatible for RK3308 USB phy
phy: phy-rockchip-inno-usb2: add support for RK3308 USB phy
dt-bindings: usb: dwc2: add compatible for RK3308 USB controller
arm64: dts: rockchip: add USB support to RK3308 dts
.../bindings/phy/rockchip-usb-phy.txt | 1 +
.../devicetree/bindings/usb/dwc2.yaml | 1 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 75 +++++++++++++++++++
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 44 +++++++++++
4 files changed, 121 insertions(+)
--
2.31.1
The Rockchip RK3308 features an integrated USB 2.0 phy, an USB OTG
controller and OHCI/EHCI interfaces.
This patch adds all of those to the RK3308 dtsi and thereby enables USB
support on the RK3308.
Signed-off-by: Tobias Schramm <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 75 ++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 0c5fa9801e6f..80fd802d6c15 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -177,6 +177,43 @@ reboot-mode {
};
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
detect_grf: syscon@ff00b000 {
compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
@@ -579,6 +616,44 @@ spdif_tx: spdif-tx@ff3a0000 {
status = "disabled";
};
+ usb20_otg: usb@ff400000 {
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
--
2.31.1
The RK3308 features a different USB phy than other Rockchip SoCs. This
patch adds a compatible string for it.
Signed-off-by: Tobias Schramm <[email protected]>
---
Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index 4ed569046daf..6547b829c27a 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -5,6 +5,7 @@ Required properties:
"rockchip,rk3066a-usb-phy"
"rockchip,rk3188-usb-phy"
"rockchip,rk3288-usb-phy"
+ "rockchip,rk3308-usb-phy"
- #address-cells: should be 1
- #size-cells: should be 0
--
2.31.1
The USB controller in the RK3308 is compatible with the RK3066 USB
controller.
This patch adds a compatible string for it.
Signed-off-by: Tobias Schramm <[email protected]>
---
Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index e5ee51b7b470..10c7d9b6cc53 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -24,6 +24,7 @@ properties:
- rockchip,rk3188-usb
- rockchip,rk3228-usb
- rockchip,rk3288-usb
+ - rockchip,rk3308-usb
- rockchip,rk3328-usb
- rockchip,rk3368-usb
- rockchip,rv1108-usb
--
2.31.1
Hi Tobias,
Just sent a patch for grf.yaml and rockchip-usb-phy.yaml conversion myself.
Added { .compatible = "rockchip,rk3308-usb2phy", .data =
&rk3308_phy_cfgs }, to phy-rockchip-inno-usb2.c
Added is "rockchip,rk3308-usb-phy" to rockchip-usb-phy.txt
compatible = "rockchip,rk3308-usb2phy"; is used in this patch.
Maybe try phy-rockchip-inno-usb2.yaml?
"rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd" document missing.
Could someone recheck the reg memory size?
Is this still correct then?
===
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x10000>;
Do we still need "0x0 0x10000" here?
===
compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xff008000 0x0 0x4000>;
===
compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
===
compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00c000 0x0 0x1000>;
===
Johan
On 5/14/21 12:27 PM, Tobias Schramm wrote:
> The Rockchip RK3308 features an integrated USB 2.0 phy, an USB OTG
> controller and OHCI/EHCI interfaces.
> This patch adds all of those to the RK3308 dtsi and thereby enables USB
> support on the RK3308.
>
> Signed-off-by: Tobias Schramm <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk3308.dtsi | 75 ++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> index 0c5fa9801e6f..80fd802d6c15 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> @@ -177,6 +177,43 @@ reboot-mode {
> };
> };
>
> + usb2phy_grf: syscon@ff008000 {
> + compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xff008000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy: usb2-phy@100 {
> + compatible = "rockchip,rk3308-usb2phy";
> + reg = <0x100 0x10>;
> + clocks = <&cru SCLK_USBPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy";
> + #clock-cells = <0>;
> + assigned-clocks = <&cru USB480M>;
> + assigned-clock-parents = <&u2phy>;
> + status = "disabled";
> +
Looks like
> + u2phy_otg: otg-port {
> + #phy-cells = <0>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "otg-bvalid", "otg-id",
> + "linestate";
> + status = "disabled";
> + };
> +
> + u2phy_host: host-port {
> + #phy-cells = <0>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "linestate";
> + status = "disabled";
> + };
> + };
> + };
> +
> detect_grf: syscon@ff00b000 {
> compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff00b000 0x0 0x1000>;
> @@ -579,6 +616,44 @@ spdif_tx: spdif-tx@ff3a0000 {
> status = "disabled";
> };
>
> + usb20_otg: usb@ff400000 {
> + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
> + "snps,dwc2";
> + reg = <0x0 0xff400000 0x0 0x40000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_OTG>;
> + clock-names = "otg";
> + dr_mode = "otg";
> + g-np-tx-fifo-size = <16>;
> + g-rx-fifo-size = <280>;
> + g-tx-fifo-size = <256 128 128 64 32 16>;
> + phys = <&u2phy_otg>;
> + phy-names = "usb2-phy";
> + status = "disabled";
> + };
> +
> + usb_host_ehci: usb@ff440000 {
> + compatible = "generic-ehci";
> + reg = <0x0 0xff440000 0x0 0x10000>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
> + clock-names = "usbhost", "arbiter", "utmi";
> + phys = <&u2phy_host>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + usb_host_ohci: usb@ff450000 {
> + compatible = "generic-ohci";
> + reg = <0x0 0xff450000 0x0 0x10000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
> + clock-names = "usbhost", "arbiter", "utmi";
> + phys = <&u2phy_host>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> sdmmc: mmc@ff480000 {
> compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xff480000 0x0 0x4000>;
>
> Hi Johan,
Am 14.05.21 um 14:09 schrieb Johan Jonker:
> Hi Tobias,
>
> Just sent a patch for grf.yaml and rockchip-usb-phy.yaml conversion myself.
>
Ah wonderful, thanks! I was not quite happy with touching the old .txt
documentation anyway. I'll adjust my next version to depend on your
patches then.
> Added { .compatible = "rockchip,rk3308-usb2phy", .data =
> &rk3308_phy_cfgs }, to phy-rockchip-inno-usb2.c
>
> Added is "rockchip,rk3308-usb-phy" to rockchip-usb-phy.txt
>
> compatible = "rockchip,rk3308-usb2phy"; is used in this patch.
>
> Maybe try phy-rockchip-inno-usb2.yaml?
>
Right. Somehow ended up in the wrong file there. Will fix it in the next
version.
> "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd" document missing.
>
> Could someone recheck the reg memory size?
> Is this still correct then?
>
> ===
> compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff000000 0x0 0x10000>;
>
> Do we still need "0x0 0x10000" here?
The technical reference manual specifies it as 64k in size. However,
since the dts has separate nodes for the other grfs it should probably
be "0x0 0x8000" at max. Technical reference manual indicates there is
nothing beyond 0x0803 in the main grf.
> ===
> compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff008000 0x0 0x4000>;
> ===
> compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff00b000 0x0 0x1000>;
> ===
> compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff00c000 0x0 0x1000>;
> ===
>
> Johan
>
> On 5/14/21 12:27 PM, Tobias Schramm wrote:
>> The Rockchip RK3308 features an integrated USB 2.0 phy, an USB OTG
>> controller and OHCI/EHCI interfaces.
>> This patch adds all of those to the RK3308 dtsi and thereby enables USB
>> support on the RK3308.
>>
>> Signed-off-by: Tobias Schramm <[email protected]>
>> ---
>> arch/arm64/boot/dts/rockchip/rk3308.dtsi | 75 ++++++++++++++++++++++++
>> 1 file changed, 75 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
>> index 0c5fa9801e6f..80fd802d6c15 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
>> @@ -177,6 +177,43 @@ reboot-mode {
>> };
>> };
>>
>> + usb2phy_grf: syscon@ff008000 {
>> + compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
>> + "simple-mfd";
>> + reg = <0x0 0xff008000 0x0 0x4000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + u2phy: usb2-phy@100 {
>
>> + compatible = "rockchip,rk3308-usb2phy";
>> + reg = <0x100 0x10>;
>> + clocks = <&cru SCLK_USBPHY_REF>;
>> + clock-names = "phyclk";
>> + clock-output-names = "usb480m_phy";
>> + #clock-cells = <0>;
>> + assigned-clocks = <&cru USB480M>;
>> + assigned-clock-parents = <&u2phy>;
>> + status = "disabled";
>> +
>
> Looks like
>
>> + u2phy_otg: otg-port {
>> + #phy-cells = <0>;
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "otg-bvalid", "otg-id",
>> + "linestate";
>> + status = "disabled";
>> + };
>> +
>> + u2phy_host: host-port {
>> + #phy-cells = <0>;
>> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "linestate";
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> detect_grf: syscon@ff00b000 {
>> compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
>> reg = <0x0 0xff00b000 0x0 0x1000>;
>> @@ -579,6 +616,44 @@ spdif_tx: spdif-tx@ff3a0000 {
>> status = "disabled";
>> };
>>
>> + usb20_otg: usb@ff400000 {
>> + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
>> + "snps,dwc2";
>> + reg = <0x0 0xff400000 0x0 0x40000>;
>> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru HCLK_OTG>;
>> + clock-names = "otg";
>> + dr_mode = "otg";
>> + g-np-tx-fifo-size = <16>;
>> + g-rx-fifo-size = <280>;
>> + g-tx-fifo-size = <256 128 128 64 32 16>;
>> + phys = <&u2phy_otg>;
>> + phy-names = "usb2-phy";
>> + status = "disabled";
>> + };
>> +
>> + usb_host_ehci: usb@ff440000 {
>> + compatible = "generic-ehci";
>> + reg = <0x0 0xff440000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
>> + clock-names = "usbhost", "arbiter", "utmi";
>> + phys = <&u2phy_host>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + usb_host_ohci: usb@ff450000 {
>> + compatible = "generic-ohci";
>> + reg = <0x0 0xff450000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
>> + clock-names = "usbhost", "arbiter", "utmi";
>> + phys = <&u2phy_host>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> sdmmc: mmc@ff480000 {
>> compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
>> reg = <0x0 0xff480000 0x0 0x4000>;
>>