The Mt. Jade BMC is an ASPEED AST2500-based BMC for the Mt. Jade
hardware reference platform with Ampere's Altra Processor family.
This series adds support PSU and OCP card on the Ampere's Mt. Jade BMC
and switch to use the 64MB flash layout as the 32MB layout will soon be
exhausted.
Quan Nguyen (3):
ARM: dts: aspeed: mtjade: Enable OCP card support via NC-SI
ARM: dts: aspeed: mtjade: Add PSU support
ARM: dts: aspeed: mtjade: switch to 64MB flash layout
.../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 57 +++++++++++++++++--
1 file changed, 53 insertions(+), 4 deletions(-)
--
2.28.0
Enable OCP card support on Ampere's Mt. Jade BMC. The Mt. Jade BMC is an
ASPEED AST2500-based BMC for the Mt. Jade hardware reference platform
with Ampere's Altra Processor Family.
Signed-off-by: Quan Nguyen <[email protected]>
Signed-off-by: Phong Vo <[email protected]>
Signed-off-by: Thang Q. Nguyen <[email protected]>
---
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
index 8f5ec22e51c2..282e901092a6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
@@ -332,6 +332,16 @@ &uart5 {
status = "okay";
};
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
&mac1 {
status = "okay";
pinctrl-names = "default";
@@ -540,7 +550,8 @@ &gpio {
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
- /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
+ /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
+ "OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
--
2.28.0
As the 32MB flash layout will soon be exhausted, switch to 64MB layout.
Signed-off-by: Quan Nguyen <[email protected]>
Signed-off-by: Phong Vo <[email protected]>
Signed-off-by: Thang Q. Nguyen <[email protected]>
---
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
index 364293e6ca76..0879f3917178 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
@@ -304,7 +304,7 @@ flash@0 {
m25p,fast-read;
label = "bmc";
/* spi-max-frequency = <50000000>; */
-#include "openbmc-flash-layout.dtsi"
+#include "openbmc-flash-layout-64.dtsi"
};
};
--
2.28.0
Enable PSU support on Ampere's Mt. Jade BMC. The Mt. Jade BMC is an
ASPEED AST2500-based BMC for the Mt. Jade hardware reference platform
with Ampere's Altra Processor Family.
Signed-off-by: Quan Nguyen <[email protected]>
Signed-off-by: Phong Vo <[email protected]>
Signed-off-by: Thang Q. Nguyen <[email protected]>
---
.../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 42 ++++++++++++++++++-
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
index 282e901092a6..364293e6ca76 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
@@ -110,6 +110,30 @@ id_button {
linux,code = <ASPEED_GPIO(Q, 5)>;
};
+ psu1_vin_good {
+ label = "PSU1_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 4)>;
+ };
+
+ psu2_vin_good {
+ label = "PSU2_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 5)>;
+ };
+
+ psu1_present {
+ label = "PSU1_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 0)>;
+ };
+
+ psu2_present {
+ label = "PSU2_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 1)>;
+ };
+
};
gpioA0mux: mux-controller {
@@ -436,6 +460,19 @@ &i2c9 {
status = "okay";
};
+&i2c10 {
+ status = "okay";
+ adm1278@10 {
+ compatible = "adi,adm1278";
+ reg = <0x10>;
+ };
+
+ adm1278@11 {
+ compatible = "adi,adm1278";
+ reg = <0x11>;
+ };
+};
+
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
@@ -539,8 +576,9 @@ &gpio {
"S1_DDR_SAVE","","",
/*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
"","",
- /*H0-H7*/ "","","","","","","","",
- /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","",
+ /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
+ /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
+ "","","","","",
/*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
"","","","",
/*K0-K7*/ "","","","","","","","",
--
2.28.0