Hi All,
This patch series adds initial support for Renesas RZ/G2L SoC and
Renesas RZ/G2L SMARC EVK.
The RZ/G2L SoC includes a single/dual Cortex-A55 CPU including
below list of IP's:
* Cortex-M33
* 3D Graphics engine (Arm Mali-G31)
* Video Codec (H.264)
* Camera interface (MIPI-CSI or Parallel-IF)
* Display interface (MIPI-DSI or Parallel-IF)
* USB2.0 interface 2ch, SD interface 2ch
* CAN interface (CAN-FD)
* Giga bit Ethernet 2ch
Initial patches enables minimal peripherals on Renesas RZ/G2L
SMARC EVK and booted via initramfs.
* Documentation for RZ/G2{L,LC,UL} SoC variants
* SoC identification support
* CPG core support
* Minimal SoC DTSi
* Minimal DTS for SMARC EVK
Patches are based on top of [1] master branch.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/
Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-
dual-core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2lc-general-purpose-microprocessors-
dual-core-arm-cortex-a55-12-ghz-cpus-3d-graphics
[*] https://renesas.info/wiki/RZ-G/RZ-G2L_SMARC
Cheers,
Prabhakar
Biju Das (1):
serial: sh-sci: Add support for RZ/G2L SoC
Lad Prabhakar (15):
dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC
dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants
dt-bindings: arm: renesas: Document SMARC EVK
soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's
arm64: defconfig: Enable ARCH_R9A07G044{L,LC}
dt-bindings: arm: renesas,prr: Add new compatible string for
RZ/G{L,LC,UL}
soc: renesas: Add support to read LSI DEVID register
soc: renesas: Add support to identify RZ/G2{L,LC} SoC's
dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
clk: renesas: Define RZ/G2L CPG Clock Definitions
clk: renesas: Add CPG core wrapper for RZ/G2L SoC
clk: renesas: Add support for R9A07G044L SoC
arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
.../devicetree/bindings/arm/renesas,prr.yaml | 6 +-
.../devicetree/bindings/arm/renesas.yaml | 18 +
.../bindings/clock/renesas,rzg2l-cpg.yaml | 80 ++
.../bindings/serial/renesas,scif.yaml | 4 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/g2l-smarc.dtsi | 27 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 70 ++
arch/arm64/boot/dts/renesas/r9a07g044l.dtsi | 21 +
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 43 +
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +
arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi | 62 ++
arch/arm64/configs/defconfig | 2 +
drivers/clk/renesas/Kconfig | 12 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r9a07g044l-cpg.c | 372 +++++++
drivers/clk/renesas/renesas-rzg2l-cpg.c | 964 ++++++++++++++++++
drivers/clk/renesas/renesas-rzg2l-cpg.h | 223 ++++
drivers/soc/renesas/Kconfig | 10 +
drivers/soc/renesas/renesas-soc.c | 33 +-
drivers/tty/serial/sh-sci.c | 11 +
drivers/tty/serial/sh-sci.h | 1 +
include/dt-bindings/clock/r9a07g044l-cpg.h | 89 ++
22 files changed, 2070 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
create mode 100644 arch/arm64/boot/dts/renesas/g2l-smarc.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
create mode 100644 drivers/clk/renesas/r9a07g044l-cpg.c
create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.c
create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.h
create mode 100644 include/dt-bindings/clock/r9a07g044l-cpg.h
--
2.17.1
RZ/G2{L,LC,UL} SoC's have LSI_DEVID register to retrieve SoC product and
revision information.
RZ/G{L,LC,UL} SoC's have 28-bit product-id compared to other R-Car and
RZ/G2{E,H,M,N} SoC's hence a new compatible string "renesas,devid" is
added.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
Documentation/devicetree/bindings/arm/renesas,prr.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
index 1f80767da38b..94afeccba29f 100644
--- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
@@ -12,14 +12,16 @@ maintainers:
description: |
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
- Register that allows to retrieve SoC product and revision information.
- If present, a device node for this register should be added.
+ Register or LSI Device ID Register that allows to retrieve SoC product
+ and revision information. If present, a device node for this register
+ should be added.
properties:
compatible:
enum:
- renesas,prr
- renesas,bsid
+ - renesas,devid
reg:
maxItems: 1
--
2.17.1
Add support for identifying the RZ/G2{L,LC} (R9A07G044{L,LC}) SoC's.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/soc/renesas/renesas-soc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index d73389670eef..23be0ddfd786 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -56,6 +56,10 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
.reg = 0xfff00044, /* PRR (Product Register) */
};
+static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
+ .name = "RZ/G2L",
+};
+
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
@@ -131,6 +135,11 @@ static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = {
.id = 0x4f,
};
+static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
+ .family = &fam_rzg2l,
+ .id = 0x841c447,
+};
+
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
@@ -299,6 +308,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A779A0
{ .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u },
#endif
+#if defined(CONFIG_ARCH_R9A07G044L) || defined(CONFIG_ARCH_R9A07G044LC)
+ { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
+#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
--
2.17.1
On Fri, 14 May 2021 20:22:08 +0100, Lad Prabhakar wrote:
> RZ/G2{L,LC,UL} SoC's have LSI_DEVID register to retrieve SoC product and
> revision information.
>
> RZ/G{L,LC,UL} SoC's have 28-bit product-id compared to other R-Car and
> RZ/G2{E,H,M,N} SoC's hence a new compatible string "renesas,devid" is
> added.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/renesas,prr.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
Hi Prabhakar,
On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/G2{L,LC,UL} SoC's have LSI_DEVID register to retrieve SoC product and
> revision information.
>
> RZ/G{L,LC,UL} SoC's have 28-bit product-id compared to other R-Car and
> RZ/G2{E,H,M,N} SoC's hence a new compatible string "renesas,devid" is
> added.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
> @@ -12,14 +12,16 @@ maintainers:
>
> description: |
> Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
> - Register that allows to retrieve SoC product and revision information.
> - If present, a device node for this register should be added.
> + Register or LSI Device ID Register that allows to retrieve SoC product
> + and revision information. If present, a device node for this register
> + should be added.
Note that this register does not seem to be documented, so I have to
trust you on this.
However, from looking at the LSI DEVID register address, this does not
seem to be a lone register (like the Product Register on other SoCs),
but to be part of the System Controller (SYSC). Hence I think there
should be separate bindings for the whole SYSC block instead.
You can still read the LSI DEVID register from renesas_soc_init(),
using the SYSC node.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds