Change-Id: Ie1618b90e77989ae558f59554d55d0d18754b091
Signed-off-by: Jitao Shi <[email protected]>
---
drivers/pwm/pwm-mtk-disp.c | 44 ++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 9c95b9af417f..d7535f24364a 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -179,8 +179,52 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return mtk_disp_pwm_enable(chip, state);
}
+static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
+ u32 clk_div, period, high_width, con0, con1;
+ u64 rate;
+ int err;
+
+ err = clk_prepare_enable(mdp->clk_main);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_main: %d\n", err);
+ return;
+ }
+ err = clk_prepare_enable(mdp->clk_mm);
+ if (err < 0) {
+ dev_err(chip->dev, "Can't enable mdp->clk_mm: %d\n", err);
+ clk_disable_unprepare(mdp->clk_main);
+ return;
+ }
+
+ rate = clk_get_rate(mdp->clk_main);
+
+ con0 = readl(mdp->base + mdp->data->con0);
+ con1 = readl(mdp->base + mdp->data->con1);
+
+ state->polarity = con0 & PWM_POLARITY ?
+ PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+ state->enabled = !!(con0 & BIT(0));
+
+ clk_div = (con0 & PWM_CLKDIV_MASK) >> PWM_CLKDIV_SHIFT;
+ period = con1 & PWM_PERIOD_MASK;
+ state->period = div_u64(period * (clk_div + 1) * NSEC_PER_SEC, rate);
+ high_width = (con1 & PWM_HIGH_WIDTH_MASK) >> PWM_HIGH_WIDTH_SHIFT;
+ state->duty_cycle = div_u64(high_width * (clk_div + 1) * NSEC_PER_SEC,
+ rate);
+
+ clk_disable_unprepare(mdp->clk_mm);
+ clk_disable_unprepare(mdp->clk_main);
+
+ mdp->enabled = state->enabled;
+}
+
static const struct pwm_ops mtk_disp_pwm_ops = {
.apply = mtk_disp_pwm_apply,
+ .get_state = mtk_disp_pwm_get_state,
.owner = THIS_MODULE,
};
--
2.25.1